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2020-10-28drivers: mux: mmio-based syscon mux controllerJean-Jacques Hiblot3-0/+157
This adds a driver for mmio-based syscon multiplexers controlled by bitfields in a syscon register range. This is heavily based on the linux mmio-mux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-10-28dm: board: complete the initialization of the muxes in initr_dm()Jean-Jacques Hiblot3-0/+47
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe" property. As a consequence they will be put in their idle state. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
2020-10-28drivers: Add a new framework for multiplexer devicesJean-Jacques Hiblot9-0/+606
Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-28Merge tag 'efi-2021-01-rc2' of ↵Tom Rini8-8/+121
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc2 A software RTC driver is supplied for UEFI SCT testing. The following UEFI related bugs are fixed: * correct handling of daylight saving time in GetTime() and SetTime() * handling of the gd register in function tracing on RISC-V * disable U-Boot devices in ExitBootServices()
2020-10-28Merge branch '2020-10-27-further-log-enhancements'Tom Rini6-12/+112
- Allow for log message continuation. - Test fix, build time error checking for new categories
2020-10-28log: correct and check array size of log categoriesHeinrich Schuchardt1-2/+8
The log command has led to NULL dereferences if an unknown category name name was used due to missing entries in the list of category names. Add compile time checks for the array sizes of log_cat_name and log_lvl_name to avoid future mishaps. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27efi_loader: daylight saving timeHeinrich Schuchardt1-3/+16
Adjust the SetTime() and GetTime() runtime services to correctly convert the daylight saving time information when communicating with the RTC. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27efi_loader: Disable devices before handing over controlIlias Apalodimas1-0/+6
U-Boot Driver Model is supposed to remove devices with either DM_REMOVE_ACTIVE_DMA or DM_REMOVE_OS_PREPARE flags set, before exiting. Our bootm command does that by explicitly calling calling "dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);" and we also disable any USB devices. The EFI equivalent is doing none of those at the moment. As a result probing an fTPM driver now renders it unusable in Linux. During our (*probe) callback we open a session with OP-TEE, which is supposed to close with our (*remove) callback. Since the (*remove) is never called, once we boot into Linux and try to probe the device again we are getting a busy error response. Moreover all uclass (*preremove) functions won't run. So let's fix this by mimicking what bootm does and disconnect devices when efi_exit_boot_services() is called. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27efi_loader: Sort header file orderingIlias Apalodimas1-4/+3
Order header files according to https://www.denx.de/wiki/U-Boot/CodingStyle Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27trace: conserve gd register on RISC-VHeinrich Schuchardt1-1/+1
An UEFI application may change the value of the register that gd lives in. But some of our functions like get_ticks() access this register. So we have to set the gd register to the U-Boot value when entering a trace point and set it back to the application value when exiting the trace point. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27rtc: provide an emulated RTCHeinrich Schuchardt4-0/+93
On a board without hardware clock this software real time clock can be used. The build time is used to initialize the RTC. So you will have to adjust the time either manually using the 'date' command or use the 'sntp' to update the RTC with the time from a network time server. See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU ticks. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27Makefile: provide constant with seconds since epochHeinrich Schuchardt1-0/+2
Provide a constant U_BOOT_EPOCH with the number of seconds since 1970-01-01. This constant can be used to initialize a software real time clock until it is updated via the 'sntp' command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27test: log: test message continuationHeinrich Schuchardt2-1/+55
Provide a unit test checking that a continuation message will use the same log level and log category as the previous message. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27log: allow for message continuationHeinrich Schuchardt4-5/+38
Some drivers use macro pr_cont() for continuing a message sent via printk. Hence if we want to convert printk messaging to using the logging system, we must support continuation of log messages too. As pr_cont() does not provide a message level we need a means of remembering the last log level. With the patch a pseudo log level LOGL_CONT as well as a pseudo log category LOGC_CONT are introduced. Using these results in the application of the same log level and category as in the previous log message. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27log: move processing_msg to global dataHeinrich Schuchardt2-4/+11
Replace the static variable processing_msg by a field in the global data. Make the field bool at it can only be true or false. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27nokia_rx51: re-enable CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENVAnatolij Gustschin1-0/+1
With disabled legacy VIDEO option CONSOLE_MUX is not auto-selected any more, re-enable it. Fixes: 9dec5a0ea130 ("nokia_rx51: disable obsolete VIDEO config") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org>
2020-10-27mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma1-4/+156
Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma1-5/+123
Define and use functions for setting input and output tapdelays based on clk phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek1-0/+85
Define input and output clock phase delays with pre-defined values. Define arasan_sdhci_clk_data type structure and add it to priv structure and store these clock phase delays in it. Read input and output clock phase delays from dt. If these values are not passed through dt, use pre-defined values. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Move macro to the topMichal Simek1-2/+2
Just group macros below headers. Other patches will be using this location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: Define timing macro'sAshok Reddy Soma3-22/+25
Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-27Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma3-1/+8
This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-27spi: zynq_qspi: Add function descriptionAshok Reddy Soma1-12/+36
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect. Fix zqspi to priv in function descriptions. Change the description of priv as pointer to zynq_qspi_priv structure. Fix other function descriptions to kernel-doc style. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27mtd: spi: Fix incorrect indentationMichal Simek1-1/+1
Use tabs to be aligned with the rest of the code. Fixes: 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27microblaze: Enable board_late_init()Michal Simek1-0/+1
In board_late_init() several variables are setup to match the current configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27microblaze: Wire generic xilinx board_late_init_xilinx()Michal Simek2-14/+5
Call generic board_late_init_xilinx() to be aligned with the rest of xilinx platforms. Also getting rid of initrd_high/fdt_high and use bootm_low/boot_size instead. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: Merge together BOOT_SCRIPT_OFFSET between MB and ARMMichal Simek3-8/+4
There is no reason not to use commong Kconfig by Microblaze too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: Remove additional newline in config filesMichal Simek3-3/+0
Trivial fix. Fixes: e519f03a1846 ("cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: Enable SF_TEST command for all ARM based platformsMichal Simek3-0/+3
Enable this command by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynq: Enable AES commandMichal Simek1-0/+1
Enable AES command to be able to use it directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynq: Change types from u32 to uint32_tMichal Simek2-2/+2
Change parameter type to avoid compilation error: In file included from ./tools/../lib/rsa/rsa-verify.c:23:0, from tools/lib/rsa/rsa-verify.c:1: include/u-boot/rsa-mod-exp.h:69:18: error: unknown type name ‘u32’; did you mean ‘__u32’? int zynq_pow_mod(u32 *keyptr, u32 *inout); ^~~ __u32 include/u-boot/rsa-mod-exp.h:69:31: error: unknown type name ‘u32’; did you mean ‘__u32’? int zynq_pow_mod(u32 *keyptr, u32 *inout); ^~~ __u32 Fixes: 37e3a36a5475 ("xilinx: zynq: Add support to secure images") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: Enable FRU command for all ARM based platformsMichal Simek3-0/+3
Enable it by default for board detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: Add DDR base address to bootscript addressT Karthik Reddy1-0/+9
Add ram base address to scriptaddr env variable to make boot script address to be a valid address when ddr base address changes. This works properly if the first memory region is the region where uboot runs. Also the solution was taken in respect of a lot of jtag script putting u-boot script to certain address. For standard cases bd->bi_dram[0].start is 0 all the time. Only for systems with DDR placed out of this location it does calculation. This is not the best solution and should be done differently in future but enough for now till we don't have full solution ready yet. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27arm64: zynqmp: Fix zynqmp mini qspi max frequencyT Karthik Reddy1-1/+1
For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynqmp: Use tab for macro indentationMichal Simek1-6/+6
Trivial fix. Fixes: fa793165daf7 ("xilinx: zynqmp: refactor silicon name function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynqmp: Do not check 0 as invalid return from snprintfMichal Simek1-1/+1
U-Boot SPL on ZynqMP is using CONFIG_SPL_USE_TINY_PRINTF which doesn't return any return value and all the time returns 0. That's why even correct snprintf was returning in SPL chip ID as "unknown". Change checking condition and allow snprintf to return 0 which is according manual patch successful return. "If an output error is encountered, a negative value is returned." Fixes: 43a138956f7e ("arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynqmp: Fix debug message in zynqmp_get_silicon_idcode_name()Michal Simek1-1/+1
Fix hex format from 0x%0X to 0x%0x to show correct numbers. Fixes: fa793165daf7 ("xilinx: zynqmp: refactor silicon name function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: zynqmp: Check return value from xilinx_pm_request()Michal Simek1-1/+5
xilinx_pm_request() can failed that's why also check return value. Fixes: 050f10f103cd ("xilinx: zynqmp: remove chip_id function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: board: Add FRU decoder supportMichal Simek1-1/+82
FMC cards are using FRU format for card identification. That's why add support for this format. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: cmd: Add basic fru format generatorMichal Simek3-2/+136
Idea is to have something what can be used for board bringup from generic board perspective. There is a violation compare to spec that FRU ID is ASCII8 instead of binary format but this is really for having something to pass boot and boot to OS which has better generating options. Also time should be filled properly. For example: fru board_gen 1000 XILINX versal-x-prc-01-revA serialX partX There is also support for revision field which is Xilinx specific field. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: cmd: Add support for FRU commandsSiva Durga Prasad Paladugu6-0/+414
This patch adds support for fru commands "fru capture" and "fru display". The fru capture parses the FRU table present at an address and stores in a structure for later use. The fru display prints the content of captured structured in a readable format. As of now, it supports only common header and board area of FRU. Also, it supports only English language code and ASCII8/BINARY formats. fru_data variable is placed to data section because fru parser can be called very early before bss is initialized. And also information needs to be shared that's why it is exported via header. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: common: Add Makefile to common folderMichal Simek4-3/+7
There is no need to reference files in common folder back. Simply adding Makefile to this folder does the job because this "common" location is already wired in main Makefile. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27microblaze: Enable i2c DM by defaultMichal Simek1-0/+1
Microblaze has been converted fully to DM that's why enabled DM for I2C too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: common: Protect board_late_init_xilinx()Michal Simek1-0/+2
Do not call board_late_init_xilinx() when BOARD_LATE_INIT is not enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board KconfigMichal Simek5-10/+23
There is no reason to have ZYNQ specific Kconfig macro in generic location to be visible for all other SoCs. That's why move it to Xilinx common location to be visible only for us. Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to disable it or enable. This has connection to code which is reading the whole content of i2c and also work with the rest of date not just with MAC address. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spl: fdt: Record load/entry fit-images entries in 64bit formatMichal Simek2-12/+8
The commit 9f45aeb93727 ("spl: fit: implement fdt_record_loadable") which introduced fdt_record_loadable() state there spl_fit.c is not 64bit safe. Based on my tests on Xilinx ZynqMP zcu102 platform there shouldn't be a problem to record these addresses in 64bit format. The patch adds support for systems which need to load images above 4GB. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27spl: Use standard FIT entriesMichal Simek5-11/+100
SPL is creating fit-images DT node when loadables are recorded in selected configuration. Entries which are created are using entry-point and load-addr property names. But there shouldn't be a need to use non standard properties because entry/load are standard FIT properties. But using standard FIT properties enables option to use generic FIT functions to descrease SPL size. Here is result for ZynqMP virt configuration: xilinx_zynqmp_virt: spl/u-boot-spl:all -82 spl/u-boot-spl:rodata -22 spl/u-boot-spl:text -60 The patch causes change in run time fit image record. Before: fit-images { uboot { os = "u-boot"; type = "firmware"; size = <0xfd520>; entry-point = <0x8000000>; load-addr = <0x8000000>; }; }; After: fit-images { uboot { os = "u-boot"; type = "firmware"; size = <0xfd520>; entry = <0x8000000>; load = <0x8000000>; }; }; Replacing calling fdt_getprop_u32() by fit_image_get_entry/load() also enables support for reading entry/load properties recorded in 64bit format. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-27spi: zynq_qspi: Use clk subsystem to get reference qspi clkT Karthik Reddy1-8/+28
Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spi: zynq_spi: Use clk subsystem to get reference spi clkT Karthik Reddy1-7/+28
Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27serial: pl01x: Add error value checkingMichal Simek1-1/+12
There also a need to check return values to make sure that clocks were enabled and setup properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 14:08:54 +0300