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2023-01-11Merge branch 'CR_3067_add_boot_hard_id_minda' into 'jh7110-master'andy.hu1-0/+1
CR_3067 dts: add boot-hart-id property in dts See merge request sdk/u-boot!24
2023-01-11configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LENYanhong Wang1-5/+5
Update the value of CONFIG_SYS_MALLOC_F_LEN from 0x8000 to 0x10000. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-09dts: add boot-hart-id property in dtsminda.chen1-0/+1
boot-hart-id is used by opensbi. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'andy.hu2-0/+20
CR_3049 dts: add i2c5 and attach pmic configuration See merge request sdk/u-boot!22
2023-01-06Merge branch 'CR_3006_OTP_yanhong.wang' into 'jh7110-master'andy.hu3-5/+14
CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read See merge request sdk/u-boot!21
2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu4-265/+490
CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110 See merge request sdk/u-boot!23
2023-01-06Merge branch 'CR_2828_perf_support_minda' into 'jh7110-master'andy.hu1-0/+46
CR_2828 dts: pmu : add riscv pmu dts config See merge request sdk/u-boot!20
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang4-265/+490
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
i2c5 and pmic is used by opensbi power management ops. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03misc: OTP: Starfive-jh7110: update the return value of starfive_otp_readYanhong Wang3-5/+14
Update the return value to match the function prototype definition. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-12-19Merge branch 'CR_2876_SET_CPU_FREQ_samin.guo' into 'jh7110-master'andy.hu2-3/+3
CR_2876: board:starfive:evb: Set the CPU default frequency to 1.0GHz See merge request sdk/u-boot!19
2022-12-16board:starfive:jh7110: Set the CPU default frequency to 1000MHzSamin Guo1-2/+2
Set to 1000M to ensure the CPU can work normally under 0.8V` voltage Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
The frequency of pll0 is set to 1000Mhz in the bootrom Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-25Merge branch 'CR_2709_pinctrl_jianlong' into 'jh7110-master'andy.hu13-28/+1518
CR_2709 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions See merge request sdk/u-boot!18
2022-11-23board:starfive:Remove usb/sdio0/sdio1 gpio initJianlong Huang1-21/+0
Remove usb/sdio0/sdio1 gpio init. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
Add pinctrl config about usb/sdio0 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21configs: Enable STARFIVE_PINCTRLJianlong Huang1-0/+4
Enable STARFIVE_PINCTRL and PINCTRL_FULL Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1028
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitionsJianlong Huang1-0/+427
Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-09Merge branch 'CR_2555_CMA_samin.guo' into 'jh7110-master'andy.hu1-4/+4
CR_2555: borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr See merge request sdk/u-boot!17
2022-11-09borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddrSamin Guo1-4/+4
The jh7110 ddr starts from 0x40000000. Using 0x80000000 may cause the CMA space to fail Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-02Merge branch 'CR_2522_ECO_EVB_samin.guo' into 'jh7110-master'andy.hu7-187/+387
CR_2522: support gamc with jh7110B-evb See merge request sdk/u-boot!16
2022-11-02driver:qspi: Switch the QSPI parent clock to pll0Samin Guo2-2/+5
Switch the QSPI parent clock to pll0 to improve the QSPI speed Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01spl:starfive:jh7110: Improved GMAC0/1 TX I/O PAD capabilitySamin Guo1-15/+30
JH7110B requires a higher IOPAD capability in 1000M mode. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: Support using env to detect board versionSamin Guo2-0/+22
JH7110B need tx_inverted by YT8521 phy, you need to read the chip version to determine whether to use it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo2-1/+29
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo2-0/+26
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters may be required in 10M/100M/1000M mode. This parameter supports JH7110B+YT8531PHY by default. Other boards can modify the parameters of the tx_inverted_10/100/1000 to obtain support. If you do not configure tx_inverted_10/100/1000 in dts, the default is 0. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dtsSamin Guo1-173/+269
support use original or inverted RGMII_TX_CLK delay train. 10M/100M/1000M can be configured independently. tx_inverted_xx = val; For example: &gmac0 { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { tx_inverted_10 = <0>; tx_inverted_100 = <1>; tx_inverted_1000 = <1>; }; }; 0: original (default) 1: inverted Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18ram: starfive: Make DDR driver support 8G sizeYan Hong Wang4-733/+547
This patch include four items: 1.rename the driver compatible name. 2.reset action with the common API. 3.clean up code to make it is closer to readable. 4.add configuration to support 8G size Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
Add reset property configuration to DDR control device tree node. Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18ram: starfive: jh7110: Replace the configuration operation for pll1 clkYan Hong Wang2-27/+6
Replace the configuration operation for pll1 clk with common api provide by pll module. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk: starfive: jh7110: Modify the parameters of clk_register()Yan Hong Wang1-34/+11
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18spl: starfive: jh7110: switch pll2 to 1188MYan Hong Wang1-165/+11
Switch the pll2 clk to 1188M with the comm pll interface on JH7110. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang4-18/+416
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18configs: starfive: fix tftpboot file waite a long time for the first timeJianlong Huang2-2/+3
ARP_TIMEOUT is too large, then will waite a long time for the first time Set ARP_TIMEOUT to 500 refer to others Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18clk:jh7110: update apb_bus clk relationshipyanhong.wang2-51/+33
The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18configs: starfive_evb_defconfig: Support saveenvJianlong Huang2-3/+5
Add saveenv config to Support saveenv Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18spl:jh7110: Modify cpu frequency should be before switching pllsamin1-3/+3
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18config:starfive-jh7110: add sd card boot configClivia.Cai1-1/+2
Configure SD card boot parameters Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
Change Model to "StarFive JH7110 EVB", and change riscv,isa to "rv64imafdcbsux" Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: Make ddr driver support 2G sizeyanhong.wang4-25/+250
The ddr driver include two configs with 2G and 4G.Fist read the ddr size config from the memory node in the dts,then match the right config and do it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive:jh7110: Delete redundant logicyanhong.wang1-28/+1
In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,one group is active high, and the other group is active low. However, the software does not need to distinguish whether the RESET signal is active high or active low,Write 1 to be assert, and write 0 to deassert. Therefore, the software does not need to add additional logic to distinguish these two sets of signals. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: pll0 dynamically gets the frequencysamin1-5/+35
pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18spl:starfive: Add support for different CPU frequencies.samin1-0/+157
The cpu uses 1.25G by default. Lists of frequencies(MHz): -375/500/625/750/875/1000/1250 -1375/1500/1625/1750/1800 Note: Some frequencies require voltage regulation. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18spl:starfive: remove function spl_cpu_fre_150/125samin1-33/+0
replace them with spl_cpu_set_rate. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang2-6/+13
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:reset:starfive-jh7110: support reset in SPLyanhong.wang2-1/+9
Update Kconfig to support reset in SPL for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:riscv:starfive: update uart3-uart5 clksyanhong.wang1-16/+24
Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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