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2021-07-15arm: ti: environment: Move <environment/ti/boot.h> in to ↵Tom Rini2-244/+228
<configs/ti_omap5_common.h> This include file is only used by ti_omap5_common.h. Further, the move is towards using the generic distro boot framework and not this set of macros. Start by moving all of the contents in directly to where they are used. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210701132612.7559-2-trini@konsulko.com
2021-07-15ti: am43xx_evm: Switch to DISTRO_BOOT onlyTom Rini6-50/+23
Remove the environment support for various legacy boot methods. With this, we will now default to booting any distribution that follows the generic distro boot framework and no longer attempt to boot various legacy (to this SoC) scripts/etc. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210701132612.7559-1-trini@konsulko.com
2021-07-15configs: am3517_evm: Fix boot hangAdam Ford1-3/+2
SPL is really tight on space, so decrease a little memory that we allocate in order to fix boot hang. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Derald D. Woods <woods.technical@gmail.com> Link: https://lore.kernel.org/r/20210626134258.601331-1-aford173@gmail.com
2021-07-15arm: omap3: Make secure_unlock_mem() staticAdam Ford1-9/+9
secure_unlock_mem() is only used in one file, so make it static in that file. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625192308.277136-4-aford173@gmail.com
2021-07-15arm: omap3: Make secureworld_exit() staticAdam Ford2-2/+1
secureworld_exit() is only used in one file, so make it static to that file and remove it from sys_proto.h. This may help with some further optimization in the future. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625192308.277136-3-aford173@gmail.com
2021-07-15arm: omap3: Make try_unlock_memory() staticAdam Ford2-9/+9
try_unlock_memory() is only used in one file, so make it static in that file,remove it from the sys_proto header file, and relocate it into the #ifdef section that call it. This will make it only built under the conditions when it is called, and it may help with some further optimization in the future. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625192308.277136-2-aford173@gmail.com
2021-07-15configs: omap3x_logic: Fix boot hang by reducing SYS_MALLOC_F_LENAdam Ford4-4/+4
The AM3517 uses SYS_MALLOC_F_LEN of size 0x3000, but the rest of the OMAP3 boards from LogicPD / BeaconEmbedded use 0x4000, but they don't boot SPL. Reduce the malloc size to restore booting. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625185717.243211-1-aford173@gmail.com
2021-07-15arm: mach-k3: am642_init: Add missing ddr guardGowtham Tammana1-1/+1
The `struct udevice *` reference is needed for either of the K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing K3_AM64_DDRSS guard. Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210624171614.14244-1-g-tammana@ti.com
2021-07-15configs: am65x_evm_a53: Enable PRUSS remoteprocLokesh Vutla1-0/+2
Enable PRUSS remoteproc driver for AM65 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-6-lokeshvutla@ti.com
2021-07-15arm: dts: ti: k3-am65-main: Add ICSSG nodesLokesh Vutla2-0/+535
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems that are present on the K3 AM65x SoCs. The three ICSSGs are identical to each other for the most part, with the ICSSG2 supporting slightly enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by a PRUSS subsystem node. These nodes are enabled by default. DT nodes are fetch from Linux 5.13 Kernel. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-5-lokeshvutla@ti.com
2021-07-15arm: dts: k3-am654-base-board: Add r5 specific u-boot dtsiLokesh Vutla3-205/+209
So far all the u-boot specific properties for both r5 and a53 are placed in k3-am654-base-board-u-boot.dtsi. But there are few a53 nodes that should be updated but doesn't belong to r5. So create a separate r5 specific u-boot dtsi. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-4-lokeshvutla@ti.com
2021-07-15remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCsKeerthy4-0/+474
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-3-lokeshvutla@ti.com
2021-07-15soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsKeerthy5-0/+457
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. Add support for pruss driver. Currently am654x family is supported. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-2-lokeshvutla@ti.com
2021-07-15arm: dts: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy ↵Aswath Govindraju1-0/+8
communication The final 128KB in SRAM is reserved by default for DMSC-lite code and secure proxy communication buffer. The memory region used for DMSC-lite code can be optionally freed up by secure firmware API[1]. However, the buffer for secure proxy communication is not configurable. This default hardware configuration is unique for AM64. Therefore, indicate the area reserved for DMSC-lite code and secure proxy communication buffer in the oc_sram device tree node. [1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210616163821.20457-3-a-govindraju@ti.com
2021-07-15configs: am64x_evm_a53_defconfig: Move TF-A load address to 0x701c0000Aswath Govindraju2-3/+3
Earlier, the region 0x701c0000 to 0x701dffff was firewalled off because of a bug in SYSFW. In the v2021.05 release of SYSFW this bug has been fixed and this region can now be used for other allocations. Therefore, move TF-A's load address to 0x701c0000 and update its location in the device tree node. Also, increase the size allocated for TF-A to account for future expansions. Fixes: defd62ca137b ("arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210616163821.20457-2-a-govindraju@ti.com
2021-07-15ti: am335x_evm: Switch to DISTRO_BOOT onlyTom Rini6-22/+6
Remove the environment support for various legacy boot methods. With this, we will now default to booting any distribution that follows the generic distro boot framework and no longer attempt to boot various legacy (to this SoC) scripts/etc. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210610230147.22475-1-trini@konsulko.com
2021-07-15configs: am335x_guardian: add register maps supportGireesh Hiremath1-0/+1
add support to direct memory access of hardware peripherals registers Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-19-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: Enable bootcount nvmem supportGireesh Hiremath1-0/+1
include bootcount nvmem support Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-18-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: software update available status is stored in AM3352 RTC ↵Gireesh Hiremath3-3/+89
scracth register RTC second scratch register[32-bit]: -zero byte hold boot count value -first byte hold update available state -second byte hold version -third byte hold magic number Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-17-Gireesh.Hiremath@in.bosch.com Gbp-Pq: Topic apertis/guardian Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch
2021-07-15am335x, guardian: Enable panel driver Himax HX8238DGireesh Hiremath6-3/+119
- Enable lcd controller - Display splash screen Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-16-Gireesh.Hiremath@in.bosch.com
2021-07-15drivers: video: hx8238 fix build bugGireesh Hiremath2-3/+3
update panel driver hx8238 fix build bug Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-15-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: Enable display configGireesh Hiremath1-3/+10
-Enable configuration for display driver -Disable support for SPL GPIO, CMD LED & SPL GPIO Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-14-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: Enable backlightGireesh Hiremath2-0/+27
Enable backlight, set brightness value and dimming frequency Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-13-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: update swi logicGireesh Hiremath2-3/+15
read boot mode gpio and set the swi status Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-12-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: disable spl commandGireesh Hiremath1-1/+1
- disable support for spl command Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-11-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: set boot delayGireesh Hiremath1-0/+1
- set boot delay to zero, to increase boot speed Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-10-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: code cleanup and boot optimizationGireesh Hiremath1-21/+0
- remove redundant headers and boot modes from board file Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-9-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: set environment variable autoload to noGireesh Hiremath1-1/+1
autoload: if set to "no" then rarpb, bootp or dhcp commands will just perform a configuration lookup from the BOOTP / DHCP server, but not try to load any image using TFTP Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-8-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: Update pinmux configurationMoses Christopher1-3/+3
pinmux update for guardian board - control ASP Board Power: GPIO, on/off ASP Board Power - control Coincell Voltage Measurement: GPIO, enable/disable ADC measurements - powerOff Device GPIO-PowerOff, cut the PMIC supply Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-7-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: add memtest configsGireesh Hiremath1-0/+4
- Add mtest, meminfo commands Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-6-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: set tftp_load_addr in environmentMoses Christopher1-0/+1
Set tftp_load_addr to 0x82000000 in MEM_LAYOUT_ENV_SETTINGS Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-5-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: add ubi fastmap supportGireesh Hiremath1-0/+1
- Trigger fastmap automatically Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-4-Gireesh.Hiremath@in.bosch.com
2021-07-15am335x, guardian: mem: Add board dependent mem valuesMoses Christopher4-1/+72
- Add mem-guardian.h derived from am33xx/mem.h * Add GPMC config values optimized for Bosch Guardian Board * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-3-Gireesh.Hiremath@in.bosch.com
2021-07-15configs: am335x_guardian: Enable clock driverGireesh Hiremath1-0/+7
Enable TI clock driver support for guardian board Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-2-Gireesh.Hiremath@in.bosch.com
2021-07-15x86: Ensure the e820 map is installed in all casesSimon Glass1-4/+4
This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15doc: Update documentation for cros-2021.04 releaseSimon Glass1-8/+7
With the new 2021.04 we have a new version of Chromium OS boot, which supports sandbox, coral and coral-on-coreboot. Add documentation for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15dtoc: Check that a parent is not missingSimon Glass3-0/+51
With of-platdata-inst we want to set up a reference to each devices' parent device, if there is one. If we find that the device has a parent (i.e. is not a root node) but it is not in the list of devices being written, then we cannot create the reference. Report an error in this case, since it indicates that the parent node is either missing a compatible string, is disabled, or perhaps does not have any properties because it was not tagged for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-15x86: cros: Check ROM exists before building vbootSimon Glass2-2/+2
All the x86 devicetree files are built at once, whichever board is actually being built. If coreboot is the target build, CONFIG_ROM_SIZE is not defined and samus cannot build Chromium OS verified boot. Add this condition to avoid errors about CONFIG_ROM_SIZE being missing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-15x86: coreboot: Document the memory mapSimon Glass1-0/+21
Add information about memory usage when U-Boot is started from coreboot. This is useful when debugging. Also, since coreboot takes a chunk of memory in the middle of SDRAM for use by PCI devices, it can help avoid overwriting this with a loaded kernel by accident. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: coreboot: Use vendor in the KconfigSimon Glass2-5/+9
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be defined TARGET_COREBOOT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Add function comments to cb_sysinfo.hSimon Glass1-0/+16
Add a function comment for get_coreboot_info() and a declaration for cb_get_sysinfo(), since this may be called from elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: coral: Allow booting from corebootSimon Glass1-0/+28
Set up coral so that it can boot from coreboot, even though it is a bare-metal build. This helps with testing since the same image can be used in both cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: coreboot: Show the BIOS dateSimon Glass1-0/+3
The BIOS version may not be present, e.g. on a Chrome OS build. Add the BIOS date as well, so we get some sort of indication of coreboot's vintage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Do cache set-up by default when booting from corebootSimon Glass1-4/+14
A recent change to disable cache setup when booting from coreboot assumed that this has been done by SPL. The result is that for the coreboot board, the cache is disabled (in start.S) and never re-enabled. If the cache was turned off, as it is on boards without SPL, we should turn it back on. Add this new condition. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Update the MP constants to avoid conflictsSimon Glass1-4/+8
These constants conflict with error codes returned by the MP implementation when something is wrong. In particular, mp_first_cpu() returns MP_SELECT_BSP when running without multiprocessing enabled. Since this is -2, it is interpreted as an error by callers, which expect a positive CPU number for the first CPU. Correct this by using a different range for the pre-defined CPU numbers, above zero and out of the range of possible CPU values. For now it is safe to assume there are no more than 64K CPUs. This fixes the 'mtrr' command when CONFIG_SMP is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Don't set up MTRRs if previously doneSimon Glass1-1/+1
When starting U-Boot from a previous-stage bootloader we presumably don't need to set up the variable MTRRs. In fact this could be harmful if the existing settings are not what U-Boot uses. Skip that step in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15tpm: cr50: Drop unnecessary coral headersSimon Glass1-2/+0
These headers are not actually used. Drop them so that this driver can be used by other boards, e.g. coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15spi: ich: Don't require the PCHSimon Glass1-2/+2
When booting from coreboot we may not have a PCH driver available. The SPI driver can operate without the PCH but currently complains in this case. Update it to continue to work normally. The only missing feature is memory-mapping of SPI-flash contents, which is not essential. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-07-15x86: pci: Allow binding of some devices before relocationSimon Glass4-3/+50
At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15pci: Use const for pci_find_device_id() etc.Simon Glass2-5/+5
These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 18:47:42 +0300