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2021-01-19Merge branch '2021-01-18-assorted-platform-updates'Tom Rini86-305/+9442
- Assorted MediaTek, AST2x00 updates - Assorted driver fixes for various platforms - Keymile platform updates - Add pwm command, mp5416 pmic driver
2021-01-18dts: mt7622: use accurate clock source fot mtk_timerWeijie Gao1-7/+1
The input system clock for mt7622 timer is 10MHz and can be retrieved through the clk driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18timer: mtk_timer: initialize the timer before useWeijie Gao1-0/+10
The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-18pinctrl: mediatek: correct error handlingHeinrich Schuchardt1-0/+1
If no GPIO controller is found, the return value should not depend on a random value on the stack. Initialize variable ret. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-01-18mtd: remove drivers/mtd/mw_eeprom.cHeinrich Schuchardt2-239/+0
drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write() and mw_eeprom_read() have incorrect loop conditions: while (len <= 2) { CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18drivers: qe: avoid double free()Heinrich Schuchardt1-1/+0
Avoid calling free(addr) twice if the device for ucode is not found. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18mmc: fsl_esdhc_spl: remove superfluous free()Heinrich Schuchardt1-3/+0
Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-18doc: board: freescale: advise to use newer atf and firmwareAndrey Zhizhikin4-24/+24
Update branch and version information of ATF and DDR firmware files to point to latest releases provided by NXP. This is especially critical for imx8mp evk, as the ATF support for that SoC is only available in latest releases. Align all SoCs from imx8m family to use identical revisions of ATF and DDR firmware. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-01-18dma: bcm6348: incorrect buffer allocationHeinrich Schuchardt1-2/+2
Calling calloc() for 0 members does not make any sense. Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally unreasonable. The current code will lead to a NULL dereference in bcm6348_iudma_enable(). The assignments for ch_priv->busy_desc are obviously swapped. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-18cmd: Add a pwm commandPragnesh Patel7-0/+174
Add the command "pwm" for controlling the pwm channels. This command provides pwm invert/config/enable/disable functionalities via PWM uclass drivers Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18power: pmic: add driver for Monolithic Power mp5416Tim Harvey4-0/+155
This adds basic register access and child regulator binding for the Monolithic MP5416 Power Management IC which integrates four DC/DC switching converters and five LDO regulators. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-01-18configs: aspeed: Add defconfig for AST2600 EVBChia-Wei, Wang2-0/+75
Add the default configuration for the AST2600 EVB. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18aspeed: Add AST2600 platform supportChia-Wei, Wang14-0/+500
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18ARM: dts: aspeed: Add AST2600 SoC supportChia-Wei, Wang4-0/+2170
AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18reset: aspeed: Add AST2600 reset supportChia-Wei, Wang4-0/+188
Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18wdt: aspeed: Add AST2600 watchdog supportChia-Wei, Wang4-0/+249
AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18ram: aspeed: Add AST2600 DRAM control supportDylan Hung4-2/+1286
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18clk: aspeed: Add AST2600 clock supportRyan Chen4-0/+1574
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18board: presidio: Add Parallel NAND supportKate Liu4-0/+57
Set environment for Nand flash (U-boot 2020.04): - add nand flash in the device tree - add new default configuration file for G3 using parallel Nand - set nand parameters in presidio_asic.h Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC supportKate Liu5-0/+1698
Add Cortina Access parallel Nand support for CAxxxx SOCs Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> CC: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18km/arm: cleanup defconfig filesHolger Brunck6-18/+31
Disable some unneeded config options and adapt the ident string. CC: Stefan Roese <sr@denx.de> Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-18km/kirkwood: enable USB support and the host controller driverHolger Brunck1-0/+4
Our kirkwood device embeds a USB host controller that is now used on some boards. This enables the support of USB and the corresponding driver. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-18mmc: Only retrieve cd pin when GPIO is enabledHarm Berntsen1-2/+4
The driver only needs to retrieve the pin for the ACPI info. The driver itself works without depending on GPIO. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18acpi: Add missing ARM acpi_table headerHarm Berntsen1-0/+0
The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h by proxy. This file does not exist for the ARM architecture and thus code compilation failed when using this driver on ARM. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18gpio: do not include <asm/arch/gpio.h> on ARCH_QEMUHarm Berntsen1-1/+2
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for QEMU. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
2021-01-18clk: mediatek: Add MT8183 clock driverFabien Parent3-0/+1153
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18tools: mtk_image: add support for booting ARM64 imagesFabien Parent2-5/+29
mkimage is only able to package aarch32 binaries. Add support for AArch64 images. One can create a ARM64 image using the following command line: mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1" -d bl2.bin bl2.img Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18configs: pumpkin: enable fastbootFabien Parent1-1/+6
Enable fastboot commands for mt8516 pumpkin board. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18configs: pumpkin: enable USB gadgetFabien Parent1-0/+8
Enable USB gadget on pumpkin. This requires to also enable BOARD_LATE_INIT since the init is done in board_late_init function. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18board: mediatek: pumpkin: initialize usb deviceFabien Parent1-0/+17
Initialize USB device on pumpkin if it is enabled in the config. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18arm: dts: mt8516-pumpkin: enable usb portFabien Parent1-0/+10
Enable the USB port for MT8516 Pumpkin Board. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18arm: dts: mt8516: add support for USBFabien Parent1-0/+14
Add support for USB on mt8516 based SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini9-13/+80
- R-Car pinctrl updates
2021-01-18Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini35-116/+2477
- Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - Select TIMER_EARLY to avoid infinite recursion for Trace.
2021-01-18Merge tag 'doc-2021-04-rc1' of ↵Tom Rini7-125/+183
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for documentation tag doc-2021-04-rc1 * document man-page base command * move README.fdt-overlays to HTML documentation * add synopsis for pstore command
2021-01-18Merge branch '2021-01-16-assorted-improvements'Tom Rini43-110/+490
- Assorted testing improvements and fixes - Assorted code cleanups
2021-01-18ARM: dts: renesas: Remove leading 0x from rpc nodeLad Prabhakar8-8/+8
Remove the leading "0x" from rpc node to fix the below dtc warning: Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit address format error, expected "ee200000" Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-01-18pinctrl: renesas: Implement get_pin_muxing() callbackLad Prabhakar1-0/+25
Implement get_pin_muxing() callback so that pinmux status command can be used on Renesas platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18pinctrl: renesas: Make sure the pin type is updated after setting the MUXLad Prabhakar1-5/+47
By default on startup all the pin types are configured to PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated when the pin is set as a function in sh_pfc_pinctrl_pin_set() or sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if the pin type is PINMUX_TYPE_NONE ie unused). So with the current implementation pin functionality could be overwritten silently, for example if the same pin is added for SPI and serial. This patch makes sure of updating pin type after every successful call to sh_pfc_config_mux() and thus fixing from pin functionality to be overwritten. Also a warning message is printed if the current pin is being overwritten before abort. This also avoids pin re-muxing to same type that is for example from command line device is asked to re-probe/select (mmc dev x) we return early with success in this case as the pin is already muxed. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18doc: board: Add Microchip MPFS Icicle Kit docPadmarao Begari3-0/+820
This doc describes the procedure to build, flash and boot Linux using U-boot on Microchip MPFS Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: Add Microchip MPFS Icicle Kit supportPadmarao Begari4-45/+145
This patch adds Microchip MPFS Icicle Kit support. For now, only NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run in S-Mode as payload of HSS + OpenSBI. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari3-0/+436
Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2021-01-18clk: Add Microchip PolarFire SoC clock driverPadmarao Begari9-0/+559
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18net: macb: Add phy address to read it from device treePadmarao Begari1-0/+13
Read phy address from device tree and use it to find the phy device if not found then search in the range of 0 to 31. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18net: macb: Add DMA 64-bit address support for macbPadmarao Begari2-17/+120
Enable 32-bit or 64-bit DMA in the macb driver based on the macb hardware compatibility and it is configured with structure macb_config in the driver. The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: Add DMA 64-bit address supportPadmarao Begari2-0/+8
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18riscv: timer: Add support for an early timerPragnesh Patel6-3/+75
Added support for timer_early_get_count() and timer_early_get_rate() This is mostly useful in tracing. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18trace: select TIMER_EARLY to avoid infinite recursionPragnesh Patel1-0/+1
When tracing functions is enabled this adds calls to __cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced functions. __cyg_profile_func_enter() and __cyg_profile_func_exit() invoke timer_get_us() to record the entry and exit time. initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an indefinite recursion. So select TIMER_EARLY when tracing got enabled. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18riscv: Add support for SPI on Kendryte K210Sean Anderson4-50/+299
This enables configs necessary for using SPI. The environment is saved to the very end of SPI flash. This is unlikely to be overwritten unless the entire flash is reprogrammed. This also supplies a default bootcommand. It loads an image and device tree from the first partition of the MMC. This is a minimal/least effort bootcmd, so suggestions (especially in the form of patches) are welcome. I didn't set up distro boot because I think it is unlikely that any general-purpose linux distros will ever be ported to this board. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Chrstopher Obbard <obbardc@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18doc: qemu-riscv: Fix opensbi build instructionsAtish Patra1-1/+1
Latest opensbi uses generic platform for Qemu. Update the build instructions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 02:21:00 +0300