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2021-01-08xea: config: Use CONFIG_PREBOOT from KconfigLukasz Majewski2-1/+2
The usage of the preboot feature is now controlled via a separate Kconfig option - namely CONFIG_USE_PREBOOT. It must be enabled for preboot code executing commands now defined in CONFIG_PREBOOT (also moved to the Kconfig). After defining both CONFIG_USE_PREBOOT and CONFIG_PREBOOT in imx28_xea_defconfig the define of CONFIG_PREBOOT shall be removed from xea.h as it is redundant. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2021-01-08xea: spl: Disable pull UP for GPIO0_2{35}Lukasz Majewski1-1/+1
On the imx287 pin GPMI_WRN (GPIO0_25) no PullUP is available that can be enabled. To get the same behavior for both boot select pins (i.e. GPIO0_2{35}) disable pull UPs on both. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2021-01-08rockchip: pinebook-pro: default to SPI bus 1 for SPI-flashHugh Cole-Baker2-4/+2
SPI flash on this machine is located on bus 1, default to using bus 1 for SPI flash and stop aliasing it to bus 0. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
2021-01-07ARM: dts: sama7g5ek: fix TXC pin configurationNicolas Ferre1-2/+6
TXC line is directly connected from the SoC to the KSZ9131 PHY. There is a transient state on this signal, before configuring it to RGMII, which leads to packet transmit being blocked. Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2021-01-07configs: sama7g5ek: add i2c and eepromEugen Hristev2-0/+6
Add drivers for flexcom, i2c and eeproms Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07board: atmel: sama7g5ek: add support for MAC address retreivalEugen Hristev1-5/+13
Obtain two MAC addresses from the two EEPROMs and configure the two available Ethernet interfaces accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: sama7g5ek: add i2c1 bus and eepromsEugen Hristev1-0/+30
Add node for flx1 i2c1 subnode (and alias to bus 0) This bus has two eeprom devices connected. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: at91: sama7g5: add flexcom1 and i2c subnodeEugen Hristev1-0/+18
Add flexcom1 and i2c subnode. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07configs: sama7g5: add mmc config for sdmmc0Eugen Hristev3-3/+72
Add new config for storing environment from sdmmc0. Also clean-up sama7g5ek_emmc1 to point to the proper mmc device. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07board: atmel: sama7g5ek: clean-up header bootcommandEugen Hristev1-8/+3
Clean-up boot command to use the predefined device and part for FAT environment. According to this device and partition, select the proper boot media. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: at91: sama7g5ek: enable sdmmc0 with pinctrlEugen Hristev1-0/+30
Enable sdmmc0 on this board. A non-removable eMMC is connected on this block. Configure pincontrol accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: at91: sama7g5: add node for sdmmc0Eugen Hristev1-0/+11
Add node for sdmmc0 block. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: at91: sama7g5: add assigned clocks for sdmmc1Eugen Hristev1-0/+3
SDMMC1 requires clock specification with assigned-clocks, such that the PMC will know which parent to assign and the initial start-up frequency. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07configs: sama7g5ek: enable CCFClaudiu Beznea1-0/+1
Enable CCF for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5ek: enable support for KSZ9131Claudiu Beznea1-0/+2
Enable support for KSZ9131. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07board: atmel: sama7g5ek: increase arp timeout and retry countClaudiu Beznea1-0/+3
Increase ARP timeout and retry count as this will increase the speed of communication. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add GMAC1Claudiu Beznea2-0/+35
Add GMAC1. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add GMAC0Claudiu Beznea2-0/+43
Add GMAC0. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5ek: enable mii commandClaudiu Beznea1-0/+1
Enable mii command as ethernet's PHY specific programming is based on it. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3Eugen Hristev2-0/+34
Add pinctrl for sdmmc1 and flx3. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: at91: sama7g5: add pinctrl nodeEugen Hristev2-0/+21
Add pioA pinctrl node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: sama7g5: add pit64b supportClaudiu Beznea2-0/+12
Add DT bindings for PIT64B driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: enable autobootClaudiu Beznea1-1/+0
Enable autoboot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5: use PIT64BClaudiu Beznea1-0/+1
Use PIT64B driver. ATMEL_PIT is not available for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add CPU bindingsClaudiu Beznea1-0/+12
Add CPU DT bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5: enable CONFIG_CPUClaudiu Beznea1-0/+1
Enable CONFIG_CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: switch to PMC bindingsClaudiu Beznea2-13/+4
Get rid of software defined MCK and switch to PMC bindings for IPs currently present in device tree. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add PMC bindingsClaudiu Beznea2-0/+13
Add DT bindings for PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add slow clock bindingsClaudiu Beznea1-0/+7
Add DT bindings for slow clock driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtalsClaudiu Beznea1-0/+8
Add dm-pre-reloc DT binding property for cristals. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: add slow rc and main rc oscillatorsClaudiu Beznea2-0/+20
Add slow rc and main rc oscillators to dtsi. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07ARM: dts: sama7g5: move clock frequencies for xtals in board fileClaudiu Beznea2-2/+10
Move clock frequencies for crystals on board specific files. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5ek: enable pll driverClaudiu Beznea1-1/+2
Enable PLL driver for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07configs: sama7g5ek: set malloc pool to 68KClaudiu Beznea1-0/+1
Set malloc pool to 68K for sama7g5ek. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07board: atmel: sama7g5ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea1-1/+2
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-07board: atmel: sama7g5ek: add initial support for sama7g5ekEugen Hristev10-0/+285
Add initial support for sama7g5 evaluation kit board. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07ARM: dts: sama7g5: add initial DT for sama7g5 SoCEugen Hristev1-0/+65
Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-07arm: at91: configs: Enable CONFIG_SYS_NAND_USE_FLASH_BBT on all boardsNicolas Ferre50-50/+0
As highlighted by Stefan in the commit e074d0f79b2e ("arm: at91: gardena-smart-gateway-at91sam: Enable CONFIG_SYS_NAND_USE_FLASH_BBT") it's important to use BBT when Linux enables it. We use it for a long time on all our boards. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Alexander Dahl <ada@thorsis.com>
2021-01-06Merge tag 'xilinx-for-v2021.04' of ↵Tom Rini25-80/+540
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
2021-01-06Merge tag 'u-boot-stm32-20210106' of ↵Tom Rini2-3/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix GPIO hog flags on DHCOM boards
2021-01-06ARM: dts: stm32: Fix GPIO hog flags on DHCOM DRC02Marek Vasut1-2/+2
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0. Since GPIO_ACTIVE_HIGH is defined as 0, this change only increases the correctness of the DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-06ARM: dts: stm32: Fix GPIO hog flags on DHCOM PicoITXMarek Vasut1-1/+1
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0. Due to a change in gpiolib-of.c, setting flags to GPIO_ACTIVE_LOW and using output-low DT property leads to the GPIO being set high instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-06Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini410-1956/+2799
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-06Merge tag 'v2021.01-rc5' into nextTom Rini445-4539/+8238
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-06Merge tag 'ti-v2021.01-rc5' of ↵Tom Rini1-2/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix I2C speed for Nokia RX51
2021-01-05dtoc: Tidy up src_scan testsSimon Glass1-6/+22
Some of these tests don't actually check anything. Add a few more checks to complete the tests. Also add a simple scan test that does the basics. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dtoc: Move src_scan tests to a separate fileSimon Glass5-78/+97
Move the tests related to scanning into their own class, updating them to avoid using dtb_platdata as a pass-through. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dtoc: Split source-code scanning to a separate fileSimon Glass3-169/+204
Before expanding the scanning features any more, move this into a separate file. This will make it easier to maintain in the future. In particular, it reduces the size of dtb_platdata.py and allows us to add tests specifically for scanning, without going through that file. The pieces moved are the Driver class, the scanning code and the various naming functions, since they mostly depend on the scanning results. So far there is are no separate tests for src_scan. These will be added as new functionality appears. This introduces no functional change. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dtoc: Drop dm_populate_phandle_data()Simon Glass5-49/+13
This has not been needed since parent information was added and we started using indicies for references to other drivers instead of pointers. It was kept around in the expectation that it might be needed later. However with the latest updates, it doesn't seem likely that we'll need this in the foreseeable future. Drop dm_populate_phandle_data() from dtoc and driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dtoc: Output nodes in orderSimon Glass2-43/+34
Previously we had to worry about nodes being output before those that they depended on, thus causing build errors. So the current algorithm is careful to output nodes in the right order. We now use a different method for outputting phandles that does not involve pointers. Also we plan to add a 'declarations' header file to declare all drivers as 'extern'. Update the code to drop the dependency checking and output in a simple loop. This makes the output easier to follow since drivers are in order of thier indices (0, 1, ...), which is also the order it appears in in the linker list. Signed-off-by: Simon Glass <sjg@chromium.org>
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