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2021-07-10board: phytec: phycore-imx8mp: Enable DVS1 controlTeresa Remmet1-1/+5
Enable DVS1 control through PMIC_STBY_REQ. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-07-10board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95VTeresa Remmet2-1/+11
Increase VDD_ARM to prevent timing issues as VDD_SOC is used in OD mode. Also increase GIC clock. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-07-10board: phytec: phycore_imx8mp: Add fec supportTeresa Remmet3-0/+38
Enable support for the fec ethernet on phyCORE-i.MX8MP. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10board: phytec: phycore_imx8mp: Change debug UARTTeresa Remmet4-13/+13
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernelTeresa Remmet2-2/+46
This update includes eqos support and some minor changes. Synced with kernel commit 412627f6ffe3 ("arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry") Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10arm: dts: imx8mp: Add common u-boot dtsiTeresa Remmet3-178/+153
Factor out the common node settings for dm-spl and dm-pre-reloc and move them to imx8mp-u-boot.dtsi Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10arm: dts: imx8mp: Resync imx8mp device tree includeTeresa Remmet1-5/+141
Sync imx8mp include with kernel commit: d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps, dwc3"") Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10pci: imx: use reset-gpios if defined by device-treeTim Harvey3-7/+27
If reset-gpio is defined by device-tree use that if CONFIG_PCIE_IMX_PERST_GPIO is not defined. Note that after this the following boards which define CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without consequence: - mx6sabresd - mx6sxsabresd - novena - tbs2910 - vining_2000 Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does not have reset-gpios defined it it's pcie node in the dt thus removing CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds reset-gpios. Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD) Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD) Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD) Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD) Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD) Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD) Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10smegw01: Select the CMD_UNZIP optionFabio Estevam1-0/+1
Select the CMD_UNZIP option so that the 'gzwrite' command can be used to flash .gz image into the eMMC. Signed-off-by: Fabio Estevam <festevam@denx.de>
2021-07-10smegw01: Allow booting the Yocto image by defaultFabio Estevam1-3/+3
On the Yocto image there is a single partition and the kernel and dtb are present in the 'boot' directory. Change it accordingly so that the board can boot the Yocto image by default. Use the generic 'load' command instead, which is able to read from an ext4 partition. Signed-off-by: Fabio Estevam <festevam@denx.de>
2021-07-10imx: ventana: display 'none' for MMC if board does not have itTim Harvey1-0/+1
print 'None' instead of just a blank line if nothing is detected: MMC: None Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: add support for DLC0700XDP21LF LCD displayTim Harvey1-0/+21
Add LVDS support for DLC0700XDP21LF 7in 1024x600 display (equivalent to the DLC-700JMGT4 with new touch controller) Signed-off-by: Robert Jones <rjones@gateworks.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: display neteowrk PHYTim Harvey1-0/+2
Add displaying the detected network PHY on boot. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: add DP83867 PHY LED configurationTim Harvey1-0/+6
Add DP83867 PHY LED configuration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: put LTC3676 regulators in continuous modeTim Harvey1-0/+6
In the default pulse-skipping mode regulators that are very lightly loaded can fail to regulate properly. Switching them to always use continuous mode causes only around 10mW of overall system power difference in a lightly loaded system that isn't already operating them in continuous mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: put PFUZ100 regulators in continuous modeTim Harvey1-0/+26
In the default 'auto' mode regulators that are very lightly loaded can be put in PFM mode and fail to regulator properly. Switching them to always use continuous PWM mode has a neglibable affect on system power and garuntees proper regulation under lightly loaded circumstances. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: add PMIC fix for GW54xx-GTim Harvey1-0/+22
Substitutions in EOL parts changes the VDD_2P5 voltage rail such that the previously unused VGEN6 LDO is needed in place of the lower power VGEN5 for the GW54xx-G. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: add legacy uboot image supportTim Harvey3-3/+0
Add Legacy U-Boot image support needed to boot a uImage. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: increase SYS_BOOTM_LENTim Harvey1-0/+3
Increase SYS_BOOM_LEN from the default 16M in imx6_common to 64M. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: remove unneeded includesTim Harvey1-14/+0
remove unnecessary includes Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx: ventana: remove USB_KEYBOARD supportTim Harvey3-3/+0
For some time now having USB_KEYBOARD support has caused usb to be initialized on boot. To allow for a quicker bootup we don't want this for Ventana and don't really need USB keyboard support so remove it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10imx8m: Restrict usable memory to space below 4G boundaryFrieder Schrempf1-0/+14
Some IPs have their accessible address space restricted by the interconnect. Let's make sure U-Boot only ever uses the space below the 4G address boundary (which is 3GiB big), even when the effective available memory is bigger. We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the whole family is affected by this. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-10clk: imx8mm: Add SPI clocksFrieder Schrempf1-1/+22
Add the clocks for the ECSPI controllers. This is ported from Linux v5.13-rc4. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-10mtd: spi-nor-ids: Add support for Macronix MX25V8035F and MX25R1635FFrieder Schrempf1-0/+2
The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very similar, but has twice the size (16Mb) and supports a wider supply voltage range. They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-10ARM: imx6: Update dhelectronics/dh_imx6/MAINTAINERS fileChristoph Niedermaier1-1/+2
Adding new DH electronics mailing list and update list of maintainers. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
2021-07-10Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini42-136/+737
Aside from the usual fixes and updates one visible change is the MMC update, which fixes some lingering bugs and gives a decent speed increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC). I am keeping an watchful eye on bug reports here, to spot any correctness regressions. Another change is finally the enablement of the first USB host port on many boards without micro-USB (data) sockets, like the Pine64 family. That doubles the number of usable USB ports from 1 to 2 on those boards. Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi) conclude this first round of changes. Compile-tested for all 157 sunxi boards, boot-tested on Pine H64, Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry. Summary: - DT update for H3/H5/H6 - Enable first USB port on boards without micro-USB - ZeroPi board support - 4GB DRAM support for H616 boards - MMC fixes and speed improvement - some fixes
2021-07-10mmc: sunxi: Use mmc_of_parse()Andre Przywara1-15/+17
At the moment the Allwinner MMC driver parses the bus-width and non-removable DT properties itself, in the probe() routine. There is actually a generic function provided by the MMC framework doing this job, also it parses more generic properties like broken-cd and advanced transfer modes. Drop our own code and call mmc_of_parse() instead, to get all new features for free. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-10mmc: sunxi: Increase MMIO FIFO read performanceAndre Przywara2-8/+32
To avoid the complexity of DMA operations (with chained descriptors), we use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us to drain or fill the MMC data buffer FIFO very easily. However those MMIO accesses are somewhat costly, so this limits our MMC performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6 (partly due to the lower AHB1 frequency). As it turns out we read the FIFO status register after *every* word we read or write, which effectively doubles the number of MMIO accesses, thus effectively more than halving our performance. To avoid this overhead, we can make use of the FIFO level bits, which are in the very same FIFO status registers. So for a read request, we now can collect as many words as the FIFO level originally indicated, and only then need to update the status register. We don't know for sure the size of the FIFO (and it seems to differ across SoCs anyway), so writing is more fragile, which is why we still use the old method for that. If we find a minimum FIFO size available on all SoCs, we could use that, in a later optimisation. This patch increases the eMMC read speed on a Pine64-LTS from about 22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s we now reach the practical limit for 3.3V SD cards. On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10mmc: sunxi: Cleanup and fix self-calibration codeAndre Przywara1-8/+19
Newer SoCs have a self calibration feature, which avoids us writing hard coded phase delay values into the controller. Consolidate the code by avoiding unnecessary #ifdefs, and also enabling the feature for all those newer SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10mmc: sunxi: Enable "new timing mode" on all new SoCsAndre Przywara1-0/+3
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so called "new timing mode", so enable this in Kconfig for those SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10mmc: sunxi: Cleanup "new timing mode" selectionAndre Przywara1-9/+6
Among the SoCs using the "new timing mode", only the A83T needs to explicitly switch to that mode. By just defining the symbol for that one odd A83T bit to 0 for any other SoCs, we can always OR that in, and save the confusing nested #ifdefs. Clean up the also confusing new_mode setting on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-10mmc: sunxi: Fix MMC clock parent selectionAndre Przywara2-4/+8
Most Allwinner SoCs which use the so called "new timing mode" in their MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their parent input clock. This is interestingly enough compensated by a hidden "by 2" post-divider in the mod clock, so the divider and actual output rate stay the same. Even though for the H6 and H616 (but only for them!) we use the doubled input clock for the divider computation, we never accounted for the implicit post-divider, so the clock was only half the speed on those SoCs. This didn't really matter so far, as our slow MMIO routine limits the transfer speed anyway, but we will fix this soon. Clean up the code around that selection, to always use the normal PLL6 (PERIPH0(1x)) clock as an input. As the rate and divider are the same, that makes no difference. Explain the hardware differences in a comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10mmc: sunxi: Fix warnings with CONFIG_PHYS_64BITAndre Przywara1-2/+2
When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which are always below 1GB on all Allwinner SoCs, so there is no problem with anything having more than 32 bits. Add the proper casts to make it compile cleanly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-10mmc: sunxi: Avoid #ifdefs in delay and width setupAndre Przywara1-18/+15
The delay and bus-width setup are slightly different across the Allwinner SoC generations, and we covered this so far with some preprocessor conditionals. Use the more readable IS_ENABLE() instead. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-10sunxi: H616: Enable full 4GB of DRAMAndre Przywara2-3/+12
The H616 is our first supported Allwinner SoC which goes beyond the 4GB address space "barrier", by having more than 32 address bits. Lift the preliminary 3GB DRAM limit for the H616, and update the page table setup on the way, to actually map that last GB as well. As not all devices are actually capable of dealing with more than 32 bits (the DMA in the EMAC for instance), we also limit U-Boot's own DRAM usage to 4GB on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10sunxi: board: Add H616 MMC2 pinsAndre Przywara1-0/+13
We hardcode the pinctrl setting for the MMC controllers in boards.c, since we need them also in the SPL, where there is no DT yet. Add the respective setting for the H616 SoC, to enable eMMC on boards with this SoC as well. Also to make diagnosing this problem easier, print a warning if a board tries to setup MMC2 pins without a respective SoC setting being defined. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan at amarulasolutions.com> Reviewed-by: Jernej Skrabec <jernej.skrabec at siol.net>
2021-07-10sunxi: h3: Add initial ZeroPi supportYu-Tung Chang4-1/+106
ZeroPi is a new board of high performance with low cost designed by FriendlyElec., using the Allwinner H3 SOC. ZeroPi features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 256MB/512MB DDR3 RAM - microsd slot - 10/100/1000Mbps Ethernet - Debug Serial Port - DC 5V/2A power-supply Signed-off-by: Yu-Tung Chang <mtwget@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10configs: OrangePi PC2: Update defaultsJernej Skrabec1-1/+3
OrangePi PC2 board has DRAM with ODT, so enable it. H5 SoC is also connected to voltage regulator. It's default value is reasonable at reset, but might be too low when rebooting with a lower voltage programmed. In order to avoid instability, enable driver for it and set it to appropriate voltage. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Andre Przywara <andre.przywara@arm.com> [Andre: remove original ZQ value change, adjust commit message] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10sunxi: clock: H6/H616: Fix PLL clock factor encodingsAndre Przywara4-5/+5
Most clock factors and dividers in the H6 PLLs use a "+1 encoding", which we were missing on two occasions. This fixes the MMC clock setup on the H6, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 Also the CPU frequency (PLL1) was a tad too high before. For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code itself, not in the bit field macro. Move this there to be aligned with what the other SoCs and other PLLs do. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2021-07-10phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSBPaul Kocialkowski1-1/+13
Recent Allwinner platforms (starting with the H3) only use the MUSB controller for peripheral mode and use HCI for host mode. As a result, extra steps need to be taken to properly route USB signals to one or the other. More precisely, the following is required: * Routing the pins to either HCI/MUSB (controlled by PHY); * Enabling USB PHY passby in HCI mode (controlled by PMU). The current code will enable passby for each PHY and reroute PHY0 to MUSB, which is inconsistent and results in broken USB peripheral support. Passby on PHY0 must only be enabled when we want to use HCI. Since host/device mode detection is not available from the PHY code and because U-Boot does not support changing the mode dynamically anyway, we can just mux the controller to MUSB if it is enabled and mux it to HCI otherwise. This fixes USB peripheral support for platforms with PHY0 dual-route, especially H3/H5 and V3s. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10arm: dts: sunxi: h3: Update DT filesAndre Przywara8-15/+142
Update the H3 DT files from the Linux 5.12 release. The changes update some boards, and don't affect U-Boot, but fix Gigabit Ethernet when this DT is passed on to the Linux kernel. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10arm: dts: sunxi: h5: Update DT filesAndre Przywara13-24/+296
Update the H5 DT files from the Linux 5.12 release. The changes don't affect U-Boot at all, but fix Gigabit Ethernet when this DT is passed on to the Linux kernel. It also introduces DVFS. This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes that are of no concern to U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10arm: dts: sunxi: h6: Update DT filesAndre Przywara6-22/+45
Update the H6 DT files from the Linux 5.12 release. The changes are minimal (many LED node renames), but also help to enable USB port 0 in U-Boot (later), enable the RSB device (not yet used in U-Boot), and also introduce an MMC frequency limit. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-09Merge branch '2021-07-09-arm-updates'Tom Rini4-14/+21
- Assorted ARM platform updates
2021-07-09Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini6-21/+198
- Support higher baudrates on Armada 3720 UART (Pali & Marek) - OcteonTX: do not require cavium BDK node to be present (Tim)
2021-07-09arm: armv8: Fix warning about redeclaring global functions as weakTom Rini1-6/+3
As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-09arm: bootm: Disable LMB reservation for command line and board info on arm64Marek Vasut1-0/+2
On arm64, board info is not applicable and kernel command line patched into the DT, so the LMB reservation here makes no sense anymore. On legacy arm32, this might still be necessary on systems which do not use DT or use legacy ATAGS. Disable this LMB reservation on arm64. This also permits Linux DT to specify reserved memory node at address close to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after boot, U-Boot will be no more, this is OK. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com>
2021-07-09arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF ↵Patrice Chotard1-6/+12
is enable Fix following compilation issue when SYS_DCACHE_OFF is enable: drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour' when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be defined. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-09armv8: Handle EL2 Host modeMark Kettenis1-2/+4
On implementations that support VHE, the layout of the CPTR_EL2 register depends on whether HCR_EL2.E2H is set. If the bit is set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact be accessed through that register. In that case, jump to the EL1 code to enable access to the FP/SIMD registers. This allows U-Boot to run on systems that pass control to U-Boot in EL2 with EL2 Host mode enabled such as machines using Apple's M1 SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Acked-by: Marc Zyngier <maz@kernel.org>
2021-07-08octeontx: do not require cavium BDK node to be presentTim Harvey1-12/+8
The cavium,bdk node is a non-standard dt node used by the BDK and therefore it is removed from the dt before booting Linux. Do not require this node to exist as it won't for standard dt's. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>