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Diffstat (limited to 'board/freescale/ls1046aqds/eth.c')
-rw-r--r--board/freescale/ls1046aqds/eth.c35
1 files changed, 25 insertions, 10 deletions
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index d3e8831f84..abe8ee95d4 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*/
#include <common.h>
@@ -153,6 +154,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
struct fixed_link f_link;
+ const u32 *handle;
+ const char *prop = NULL;
+ int off;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
switch (port) {
@@ -208,16 +212,27 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
(port == FM1_10GEC1 || port == FM1_10GEC2)) {
- /* XFI interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(10000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+ handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
+ prop = NULL;
+ if (handle) {
+ off = fdt_node_offset_by_phandle(fdt,
+ fdt32_to_cpu(*handle));
+ prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
+ }
+ if (!prop || strcmp(prop, "10gbase-kr")) {
+ /* XFI interface */
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(10000);
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "xgmii");
+ }
}
}