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path: root/arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h
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Diffstat (limited to 'arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h')
-rw-r--r--arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h386
1 files changed, 386 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h b/arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h
new file mode 100644
index 0000000000..9a2a7aa811
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7100/vout_sys_clkgen_ctrl_macro.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+/******************************************************************
+*
+* vout_sys_clkgen controller C MACRO generated by ezchip
+*
+******************************************************************/
+
+#ifndef _VOUT_SYS_CLKGEN_MACRO_H_
+#define _VOUT_SYS_CLKGEN_MACRO_H_
+
+//#define VOUT_SYS_CLKGEN_BASE_ADDR 0x0
+#define clk_vout_apb_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x0
+#define clk_mapconv_apb_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x4
+#define clk_mapconv_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x8
+#define clk_disp0_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0xC
+#define clk_disp1_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x10
+#define clk_lcdc_oclk_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x14
+#define clk_lcdc_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x18
+#define clk_vpp0_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x1C
+#define clk_vpp1_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x20
+#define clk_vpp2_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x24
+#define clk_pixrawout_apb_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x28
+#define clk_pixrawout_axi_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x2C
+#define clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x30
+#define clk_csi2tx_strm0_apb_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x34
+#define clk_dsi_sys_clk_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x38
+#define clk_dsi_apb_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x3C
+#define clk_ppi_tx_esc_clk_ctrl_REG_ADDR VOUT_SYS_CLKGEN_BASE_ADDR + 0x40
+
+#define _ENABLE_CLOCK_clk_vout_apb_ {}
+
+#define _DIVIDE_CLOCK_clk_vout_apb_(div) { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0xF); \
+ _ezchip_macro_read_value_ |= (div&0xF); \
+ MA_OUTW(clk_vout_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_DIVIDE_STATUS_clk_vout_apb_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_vout_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= 0xf;\
+}
+
+#define _ENABLE_CLOCK_clk_mapconv_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_mapconv_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_mapconv_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_mapconv_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_mapconv_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_mapconv_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_mapconv_apb_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_mapconv_apb_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_mapconv_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_mapconv_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_mapconv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_mapconv_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_mapconv_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_mapconv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_mapconv_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_mapconv_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_disp0_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp0_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_disp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_disp0_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp0_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_disp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_disp0_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_disp0_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_disp1_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp1_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_disp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_disp1_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp1_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_disp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_disp1_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_disp1_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_lcdc_oclk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_lcdc_oclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_lcdc_oclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_lcdc_oclk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_lcdc_oclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_lcdc_oclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_lcdc_oclk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_lcdc_oclk_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _DIVIDE_CLOCK_clk_lcdc_oclk_(div) { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_lcdc_oclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x3F); \
+ _ezchip_macro_read_value_ |= (div&0x3F); \
+ MA_OUTW(clk_lcdc_oclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_DIVIDE_STATUS_clk_lcdc_oclk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_lcdc_oclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= 0x3f;\
+}
+
+#define _ENABLE_CLOCK_clk_lcdc_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_lcdc_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_lcdc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_lcdc_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_lcdc_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_lcdc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_lcdc_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_lcdc_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_vpp0_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp0_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_vpp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_vpp0_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp0_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_vpp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_vpp0_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_vpp0_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_vpp1_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp1_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_vpp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_vpp1_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp1_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_vpp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_vpp1_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_vpp1_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_vpp2_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp2_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_vpp2_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_vpp2_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_vpp2_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_vpp2_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_vpp2_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_vpp2_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_pixrawout_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_pixrawout_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_pixrawout_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_pixrawout_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_pixrawout_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_pixrawout_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_pixrawout_apb_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_pixrawout_apb_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_pixrawout_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_pixrawout_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_pixrawout_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_pixrawout_axi_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_pixrawout_axi_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_pixrawout_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_pixrawout_axi_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_pixrawout_axi_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_csi2tx_strm0_pixclk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_csi2tx_strm0_pixclk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_csi2tx_strm0_pixclk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _DIVIDE_CLOCK_clk_csi2tx_strm0_pixclk_(div) { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x3F); \
+ _ezchip_macro_read_value_ |= (div&0x3F); \
+ MA_OUTW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_DIVIDE_STATUS_clk_csi2tx_strm0_pixclk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_pixclk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= 0x3f;\
+}
+
+#define _ENABLE_CLOCK_clk_csi2tx_strm0_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_csi2tx_strm0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_csi2tx_strm0_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_csi2tx_strm0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_csi2tx_strm0_apb_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_csi2tx_strm0_apb_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_dsi_sys_clk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsi_sys_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_dsi_sys_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_dsi_sys_clk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsi_sys_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_dsi_sys_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_dsi_sys_clk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_dsi_sys_clk_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_dsi_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsi_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_dsi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_dsi_apb_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsi_apb_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_dsi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_dsi_apb_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_dsi_apb_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _ENABLE_CLOCK_clk_ppi_tx_esc_clk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
+ MA_OUTW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _DISABLE_CLOCK_clk_ppi_tx_esc_clk_ { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x1<<31); \
+ _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
+ MA_OUTW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_ENABLE_STATUS_clk_ppi_tx_esc_clk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR) >> 31; \
+ _ezchip_macro_read_value_ &= 0x1;\
+}
+
+#define _DIVIDE_CLOCK_clk_ppi_tx_esc_clk_(div) { \
+ uint32_t _ezchip_macro_read_value_=MA_INW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= ~(0x7F); \
+ _ezchip_macro_read_value_ |= (div&0x7F); \
+ MA_OUTW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
+}
+
+#define _GET_CLOCK_DIVIDE_STATUS_clk_ppi_tx_esc_clk_(_ezchip_macro_read_value_) { \
+ _ezchip_macro_read_value_=MA_INW(clk_ppi_tx_esc_clk_ctrl_REG_ADDR); \
+ _ezchip_macro_read_value_ &= 0x7f;\
+}
+
+#endif //_VOUT_SYS_CLKGEN_MACRO_H_
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-21 05:29:12 +0300