diff options
Diffstat (limited to 'arch/riscv/include/asm/arch-jh7100/syscon_simu_test_macro.h')
| -rw-r--r-- | arch/riscv/include/asm/arch-jh7100/syscon_simu_test_macro.h | 223 |
1 files changed, 223 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7100/syscon_simu_test_macro.h b/arch/riscv/include/asm/arch-jh7100/syscon_simu_test_macro.h new file mode 100644 index 0000000000..9fbe96fb5b --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7100/syscon_simu_test_macro.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/****************************************************************** +* +* syscon_simu_test_top C MACRO generated by ezchip +* +******************************************************************/ + +#ifndef _SYSCON_SIMU_TEST_MACRO_H_ +#define _SYSCON_SIMU_TEST_MACRO_H_ + +//#define SYSCON_SIMU_TEST_BASE_ADDR 0x0 +#define syscon_simu_test_register0_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x4 +#define syscon_simu_test_register1_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x8 +#define syscon_simu_test_register2_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0xC +#define syscon_simu_test_register3_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x10 +#define syscon_simu_test_register4_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x14 +#define syscon_simu_test_register5_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x18 +#define syscon_simu_test_register6_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x1C +#define syscon_simu_test_register7_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x20 +#define syscon_simu_test_register8_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x24 +#define syscon_simu_test_register9_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x28 +#define syscon_simu_test_register10_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x2C +#define syscon_simu_test_register11_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x30 +#define syscon_simu_test_register12_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x34 +#define syscon_simu_test_register13_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x38 +#define syscon_simu_test_register14_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x3C +#define syscon_simu_test_register15_REG_ADDR SYSCON_SIMU_TEST_BASE_ADDR + 0x40 + +#define _SET_SYSCON_REG_register0_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register0_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register0_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register0_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register0_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register1_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register1_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register1_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register1_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register1_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register2_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register2_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register2_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register2_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register2_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register3_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register3_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register3_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register3_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register3_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register4_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register5_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register6_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register6_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register6_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register7_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register7_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register7_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register7_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register7_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register8_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register8_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register8_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register8_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register8_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register9_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register9_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register9_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register9_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register9_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register10_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register10_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register10_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register10_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register10_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register11_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register11_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register11_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register11_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register11_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register12_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register12_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register12_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register12_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register12_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register13_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register13_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register13_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register13_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register13_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register14_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register15_simu_debug(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(syscon_simu_test_register15_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register15_simu_debug(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(syscon_simu_test_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#endif //_SYSCON_SIMU_TEST_MACRO_H_ |