diff options
Diffstat (limited to 'arch/riscv/include/asm/arch-jh7100/isp_syscontroller_macro.h')
| -rw-r--r-- | arch/riscv/include/asm/arch-jh7100/isp_syscontroller_macro.h | 1381 |
1 files changed, 1381 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7100/isp_syscontroller_macro.h b/arch/riscv/include/asm/arch-jh7100/isp_syscontroller_macro.h new file mode 100644 index 0000000000..fce8c785e5 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7100/isp_syscontroller_macro.h @@ -0,0 +1,1381 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/****************************************************************** +* +* isp_syscontroller_top C MACRO generated by ezchip +* +******************************************************************/ + +#ifndef _ISP_SYSCONTROLLER_MACRO_H_ +#define _ISP_SYSCONTROLLER_MACRO_H_ + +//#define ISP_SYSCONTROLLER_BASE_ADDR 0x0 +#define isp_syscontroller_register0_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x0 +#define isp_syscontroller_register1_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x4 +#define isp_syscontroller_register2_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x8 +#define isp_syscontroller_register3_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xC +#define isp_syscontroller_register4_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x10 +#define isp_syscontroller_register5_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x14 +#define isp_syscontroller_register6_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x18 +#define isp_syscontroller_register7_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x1C +#define isp_syscontroller_register8_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x20 +#define isp_syscontroller_register9_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x24 +#define isp_syscontroller_register10_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x28 +#define isp_syscontroller_register11_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x2C +#define isp_syscontroller_register12_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x30 +#define isp_syscontroller_register13_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x34 +#define isp_syscontroller_register14_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x38 +#define isp_syscontroller_register15_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x3C +#define isp_syscontroller_register16_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x40 +#define isp_syscontroller_register17_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x44 +#define isp_syscontroller_register18_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x48 +#define isp_syscontroller_register19_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x4C +#define isp_syscontroller_register20_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x50 +#define isp_syscontroller_register21_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x54 +#define isp_syscontroller_register22_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x58 +#define isp_syscontroller_register23_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x5C +#define isp_syscontroller_register24_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x60 +#define isp_syscontroller_register25_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x64 +#define isp_syscontroller_register26_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x68 +#define isp_syscontroller_register27_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x6C +#define isp_syscontroller_register28_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x70 +#define isp_syscontroller_register29_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x74 +#define isp_syscontroller_register30_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x78 +#define isp_syscontroller_register31_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x7C +#define isp_syscontroller_register32_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x80 +#define isp_syscontroller_register33_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x84 +#define isp_syscontroller_register34_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x88 +#define isp_syscontroller_register35_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x8C +#define isp_syscontroller_register36_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x90 +#define isp_syscontroller_register37_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x94 +#define isp_syscontroller_register38_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x98 +#define isp_syscontroller_register39_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0x9C +#define isp_syscontroller_register40_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xA0 +#define isp_syscontroller_register41_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xA4 +#define isp_syscontroller_register42_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xA8 +#define isp_syscontroller_register43_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xAC +#define isp_syscontroller_register44_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xB0 +#define isp_syscontroller_register45_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xB4 +#define isp_syscontroller_register46_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xB8 +#define isp_syscontroller_register47_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xBC +#define isp_syscontroller_register48_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xC0 +#define isp_syscontroller_register49_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xC4 +#define isp_syscontroller_register50_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xC8 +#define isp_syscontroller_register51_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xCC +#define isp_syscontroller_register52_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xD0 +#define isp_syscontroller_register53_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xD4 +#define isp_syscontroller_register54_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xD8 +#define isp_syscontroller_register55_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xDC +#define isp_syscontroller_register56_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xE0 +#define isp_syscontroller_register57_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xE4 +#define isp_syscontroller_register58_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xE8 +#define isp_syscontroller_register59_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xEC +#define isp_syscontroller_register60_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xF0 +#define isp_syscontroller_register61_REG_ADDR ISP_SYSCONTROLLER_BASE_ADDR + 0xF4 + +#define _SET_SYSCON_REG_register0_test_generic_status(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register0_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFF); \ + MA_OUTW(isp_syscontroller_register0_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register0_test_generic_status(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register0_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xffff;\ +} + +#define _SET_SYSCON_REG_register0_test_generic_status1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register0_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFF<<16); \ + _ezchip_macro_read_value_ |= (v&0xFFFF)<<16; \ + MA_OUTW(isp_syscontroller_register0_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register0_test_generic_status1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register0_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0xffff;\ +} + +#define _GET_SYSCON_REG_register1_test_generic_ctrl(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register1_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xffff;\ +} + +#define _GET_SYSCON_REG_register1_test_generic_ctrl1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register1_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0xffff;\ +} + +#define _GET_SYSCON_REG_register2_generic_sp(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register2_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3ff;\ +} + +#define _GET_SYSCON_REG_register2_generic_sp1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register2_REG_ADDR) >> 10; \ + _ezchip_macro_read_value_ &= 0x3ff;\ +} + +#define _SET_SYSCON_REG_register3_SCFG_sram_cofig(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register3_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3); \ + _ezchip_macro_read_value_ |= (v&0x3); \ + MA_OUTW(isp_syscontroller_register3_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register3_SCFG_sram_cofig(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register3_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register4_rx_1c2c_sel(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1); \ + _ezchip_macro_read_value_ |= (v&0x1); \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_rx_1c2c_sel(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_clk(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<1); \ + _ezchip_macro_read_value_ |= (v&0x7)<<1; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_clk(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 1; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_clk1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<4); \ + _ezchip_macro_read_value_ |= (v&0x7)<<4; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_clk1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 4; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_lan0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<7); \ + _ezchip_macro_read_value_ |= (v&0x7)<<7; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_lan0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 7; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_lan1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<10); \ + _ezchip_macro_read_value_ |= (v&0x7)<<10; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_lan1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 10; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_lan2(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<13); \ + _ezchip_macro_read_value_ |= (v&0x7)<<13; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_lan2(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 13; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_lane_swap_lan3(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7<<16); \ + _ezchip_macro_read_value_ |= (v&0x7)<<16; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_lane_swap_lan3(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0x7;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_clk(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<19); \ + _ezchip_macro_read_value_ |= (v&0x1)<<19; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_clk(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 19; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_clk1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<20); \ + _ezchip_macro_read_value_ |= (v&0x1)<<20; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_clk1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 20; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_lan0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<21); \ + _ezchip_macro_read_value_ |= (v&0x1)<<21; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_lan0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 21; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_lan1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<22); \ + _ezchip_macro_read_value_ |= (v&0x1)<<22; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_lan1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 22; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_lan2(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<23); \ + _ezchip_macro_read_value_ |= (v&0x1)<<23; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_lan2(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 23; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_dpdn_swap_lan3(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<24); \ + _ezchip_macro_read_value_ |= (v&0x1)<<24; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_dpdn_swap_lan3(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 24; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_hs_freq_change_clk(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<25); \ + _ezchip_macro_read_value_ |= (v&0x1)<<25; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_hs_freq_change_clk(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 25; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register4_hs_freq_change_clk1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<26); \ + _ezchip_macro_read_value_ |= (v&0x1)<<26; \ + MA_OUTW(isp_syscontroller_register4_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register4_hs_freq_change_clk1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register4_REG_ADDR) >> 26; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register5_gpi_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3F); \ + _ezchip_macro_read_value_ |= (v&0x3F); \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_gpi_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3f;\ +} + +#define _SET_SYSCON_REG_register5_mp_test_mode_sel(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1F<<6); \ + _ezchip_macro_read_value_ |= (v&0x1F)<<6; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_mp_test_mode_sel(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 6; \ + _ezchip_macro_read_value_ &= 0x1f;\ +} + +#define _SET_SYSCON_REG_register5_mp_test_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<11); \ + _ezchip_macro_read_value_ |= (v&0x1)<<11; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_mp_test_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 11; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register5_dphy_enable_lan0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<12); \ + _ezchip_macro_read_value_ |= (v&0x1)<<12; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_dphy_enable_lan0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 12; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register5_dphy_enable_lan1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<13); \ + _ezchip_macro_read_value_ |= (v&0x1)<<13; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_dphy_enable_lan1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 13; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register5_dphy_enable_lan2(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<14); \ + _ezchip_macro_read_value_ |= (v&0x1)<<14; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_dphy_enable_lan2(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 14; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register5_dphy_enable_lan3(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<15); \ + _ezchip_macro_read_value_ |= (v&0x1)<<15; \ + MA_OUTW(isp_syscontroller_register5_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register5_dphy_enable_lan3(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register5_REG_ADDR) >> 15; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register6_cnfg_axi_dvp_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1); \ + _ezchip_macro_read_value_ |= (v&0x1); \ + MA_OUTW(isp_syscontroller_register6_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register6_cnfg_axi_dvp_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register6_cnfg_axi_wr_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<1); \ + _ezchip_macro_read_value_ |= (v&0x1)<<1; \ + MA_OUTW(isp_syscontroller_register6_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register6_cnfg_axi_wr_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR) >> 1; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register6_cnfg_gen_en_axird(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<2); \ + _ezchip_macro_read_value_ |= (v&0x1)<<2; \ + MA_OUTW(isp_syscontroller_register6_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register6_cnfg_gen_en_axird(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register6_REG_ADDR) >> 2; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register7_cnfg_axird_start_addr(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register7_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register7_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register7_cnfg_axird_start_addr(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register7_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register8_cnfg_axird_end_addr(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register8_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register8_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register8_cnfg_axird_end_addr(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register8_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register9_cnfg_axiwr_channel_sel(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register9_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xF); \ + _ezchip_macro_read_value_ |= (v&0xF); \ + MA_OUTW(isp_syscontroller_register9_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register9_cnfg_axiwr_channel_sel(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register9_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xf;\ +} + +#define _SET_SYSCON_REG_register10_cnfg_axiwr_start_addr(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register10_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register10_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register10_cnfg_axiwr_start_addr(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register10_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register11_cnfg_axiwr_end_addr(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register11_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register11_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register11_cnfg_axiwr_end_addr(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register11_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register12_cnfg_axiwr_pix_cnt_end(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register12_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7FF); \ + _ezchip_macro_read_value_ |= (v&0x7FF); \ + MA_OUTW(isp_syscontroller_register12_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register12_cnfg_axiwr_pix_cnt_end(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register12_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x7ff;\ +} + +#define _SET_SYSCON_REG_register13_cnfg_axird_axi_cnt_end(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register13_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x7FF); \ + _ezchip_macro_read_value_ |= (v&0x7FF); \ + MA_OUTW(isp_syscontroller_register13_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register13_cnfg_axird_axi_cnt_end(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register13_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x7ff;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_axiwr_pix_ct(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3); \ + _ezchip_macro_read_value_ |= (v&0x3); \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_axiwr_pix_ct(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_axird_pix_ct(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3<<2); \ + _ezchip_macro_read_value_ |= (v&0x3)<<2; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_axird_pix_ct(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 2; \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_pix_num(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xF<<4); \ + _ezchip_macro_read_value_ |= (v&0xF)<<4; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_pix_num(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 4; \ + _ezchip_macro_read_value_ &= 0xf;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_dvp_vs_pos(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<8); \ + _ezchip_macro_read_value_ |= (v&0x1)<<8; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_dvp_vs_pos(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 8; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_dvp_hs_pos(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<9); \ + _ezchip_macro_read_value_ |= (v&0x1)<<9; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_dvp_hs_pos(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 9; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_dvp_swap_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<10); \ + _ezchip_macro_read_value_ |= (v&0x1)<<10; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_dvp_swap_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 10; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_axiwr_pixel_high_bit_sel(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3<<12); \ + _ezchip_macro_read_value_ |= (v&0x3)<<12; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_axiwr_pixel_high_bit_sel(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 12; \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register14_cnfg_color_bar_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<16); \ + _ezchip_macro_read_value_ |= (v&0x1)<<16; \ + MA_OUTW(isp_syscontroller_register14_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register14_cnfg_color_bar_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register14_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register15_cnfg_mipi_channel_sel0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xF); \ + _ezchip_macro_read_value_ |= (v&0xF); \ + MA_OUTW(isp_syscontroller_register15_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register15_cnfg_mipi_channel_sel0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xf;\ +} + +#define _SET_SYSCON_REG_register15_cnfg_mipi_channel_sel1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xF<<4); \ + _ezchip_macro_read_value_ |= (v&0xF)<<4; \ + MA_OUTW(isp_syscontroller_register15_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register15_cnfg_mipi_channel_sel1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR) >> 4; \ + _ezchip_macro_read_value_ &= 0xf;\ +} + +#define _SET_SYSCON_REG_register15_cnfg_axi_dvp_en0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<8); \ + _ezchip_macro_read_value_ |= (v&0x1)<<8; \ + MA_OUTW(isp_syscontroller_register15_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register15_cnfg_axi_dvp_en0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR) >> 8; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register15_cnfg_axi_dvp_en1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<12); \ + _ezchip_macro_read_value_ |= (v&0x1)<<12; \ + MA_OUTW(isp_syscontroller_register15_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register15_cnfg_axi_dvp_en1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register15_REG_ADDR) >> 12; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register16_cnfg_mipi_byte_en_isp0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3); \ + _ezchip_macro_read_value_ |= (v&0x3); \ + MA_OUTW(isp_syscontroller_register16_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register16_cnfg_mipi_byte_en_isp0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register16_cnfg_mipi_byte_en_isp1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3<<2); \ + _ezchip_macro_read_value_ |= (v&0x3)<<2; \ + MA_OUTW(isp_syscontroller_register16_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register16_cnfg_mipi_byte_en_isp1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR) >> 2; \ + _ezchip_macro_read_value_ &= 0x3;\ +} + +#define _SET_SYSCON_REG_register16_cnfg_p_i_mipi_header_en0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<4); \ + _ezchip_macro_read_value_ |= (v&0x1)<<4; \ + MA_OUTW(isp_syscontroller_register16_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register16_cnfg_p_i_mipi_header_en0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR) >> 4; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register16_cnfg_p_i_mipi_header_en1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<5); \ + _ezchip_macro_read_value_ |= (v&0x1)<<5; \ + MA_OUTW(isp_syscontroller_register16_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register16_cnfg_p_i_mipi_header_en1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register16_REG_ADDR) >> 5; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register17_cnfg_axird_line_cnt_start(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register17_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFF); \ + MA_OUTW(isp_syscontroller_register17_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register17_cnfg_axird_line_cnt_start(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register17_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xfff;\ +} + +#define _SET_SYSCON_REG_register18_cnfg_axird_line_cnt_end(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register18_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFF); \ + MA_OUTW(isp_syscontroller_register18_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register18_cnfg_axird_line_cnt_end(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register18_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xfff;\ +} + +#define _SET_SYSCON_REG_register19_cnfg_axird_pix_cnt_start(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register19_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1FFF); \ + _ezchip_macro_read_value_ |= (v&0x1FFF); \ + MA_OUTW(isp_syscontroller_register19_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register19_cnfg_axird_pix_cnt_start(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register19_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1fff;\ +} + +#define _SET_SYSCON_REG_register20_cnfg_axird_pix_cnt_end(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register20_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1FFF); \ + _ezchip_macro_read_value_ |= (v&0x1FFF); \ + MA_OUTW(isp_syscontroller_register20_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register20_cnfg_axird_pix_cnt_end(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register20_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1fff;\ +} + +#define _SET_SYSCON_REG_register21_cnfg_axiwr_intr_clean(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1); \ + _ezchip_macro_read_value_ |= (v&0x1); \ + MA_OUTW(isp_syscontroller_register21_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register21_cnfg_axiwr_intr_clean(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register21_cnfg_axiwr_intr_mask(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<4); \ + _ezchip_macro_read_value_ |= (v&0x1)<<4; \ + MA_OUTW(isp_syscontroller_register21_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register21_cnfg_axiwr_intr_mask(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR) >> 4; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register21_cnfg_axird_intr_clean(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<16); \ + _ezchip_macro_read_value_ |= (v&0x1)<<16; \ + MA_OUTW(isp_syscontroller_register21_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register21_cnfg_axird_intr_clean(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register21_cnfg_axird_intr_mask(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<20); \ + _ezchip_macro_read_value_ |= (v&0x1)<<20; \ + MA_OUTW(isp_syscontroller_register21_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register21_cnfg_axird_intr_mask(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register21_REG_ADDR) >> 20; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register22_dphy_XCFGI_0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register22_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register22_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register22_dphy_XCFGI_0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register22_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register23_dphy_XCFGI_1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register23_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register23_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register23_dphy_XCFGI_1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register23_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register24_dphy_XCFGI_2(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register24_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register24_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register24_dphy_XCFGI_2(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register24_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register25_dphy_XCFGI_3(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register25_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register25_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register25_dphy_XCFGI_3(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register25_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register26_dphy_XCFGI_4(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register26_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register26_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register26_dphy_XCFGI_4(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register26_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register27_dphy_XCFGI_5(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register27_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register27_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register27_dphy_XCFGI_5(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register27_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register28_dphy_XCFGI_6(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register28_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register28_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register28_dphy_XCFGI_6(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register28_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register29_dphy_XCFGI_7(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register29_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register29_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register29_dphy_XCFGI_7(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register29_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register30_dphy_XCFGI_8(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register30_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register30_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register30_dphy_XCFGI_8(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register30_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register31_dphy_XCFGI_9(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register31_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register31_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register31_dphy_XCFGI_9(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register31_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register32_dphy_XCFGI_10(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register32_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register32_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register32_dphy_XCFGI_10(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register32_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register33_dphy_XCFGI_11(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register33_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register33_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register33_dphy_XCFGI_11(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register33_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register34_dphy_XCFGI_12(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register34_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register34_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register34_dphy_XCFGI_12(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register34_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register35_dphy_XCFGI_13(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register35_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register35_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register35_dphy_XCFGI_13(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register35_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register36_dphy_XCFGI_14(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register36_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register36_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register36_dphy_XCFGI_14(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register36_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register37_dphy_XCFGI_15(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register37_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register37_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register37_dphy_XCFGI_15(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register37_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register38_dphy_XCFGI_16(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register38_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register38_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register38_dphy_XCFGI_16(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register38_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register39_dphy_XCFGI_17(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register39_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register39_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register39_dphy_XCFGI_17(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register39_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register40_dphy_XCFGI_18(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register40_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register40_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register40_dphy_XCFGI_18(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register40_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register41_dphy_XCFGI_19(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register41_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register41_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register41_dphy_XCFGI_19(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register41_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register42_dphy_XCFGI_20(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register42_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register42_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register42_dphy_XCFGI_20(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register42_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register43_dphy_XCFGI_21(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register43_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register43_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register43_dphy_XCFGI_21(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register43_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register44_dphy_XCFGI_22(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register44_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register44_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register44_dphy_XCFGI_22(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register44_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register45_dphy_XCFGI_23(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register45_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register45_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register45_dphy_XCFGI_23(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register45_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register46_dphy_XCFGI_24(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register46_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register46_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register46_dphy_XCFGI_24(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register46_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register47_dphy_XCFGI_25(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register47_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register47_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register47_dphy_XCFGI_25(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register47_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register48_dphy_XCFGI_26(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register48_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register48_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register48_dphy_XCFGI_26(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register48_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register49_dphy_XCFGI_27(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register49_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register49_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register49_dphy_XCFGI_27(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register49_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register50_dphy_XCFGI_28(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register50_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register50_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register50_dphy_XCFGI_28(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register50_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register51_dphy_XCFGI_29(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register51_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register51_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register51_dphy_XCFGI_29(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register51_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register52_dphy_XCFGI_30(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register52_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register52_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register52_dphy_XCFGI_30(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register52_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register53_dphy_XCFGI_31(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register53_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register53_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register53_dphy_XCFGI_31(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register53_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register54_dphy_XCFGI_32(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register54_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register54_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register54_dphy_XCFGI_32(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register54_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register55_dphy_XCFGI_33(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register55_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register55_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register55_dphy_XCFGI_33(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register55_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register56_dphy_XCFGI_34(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register56_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \ + MA_OUTW(isp_syscontroller_register56_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register56_dphy_XCFGI_34(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register56_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xFFFFFFFF;\ +} + +#define _SET_SYSCON_REG_register57_dphy_XCFGI_35(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register57_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFFFF); \ + _ezchip_macro_read_value_ |= (v&0xFFFF); \ + MA_OUTW(isp_syscontroller_register57_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register57_dphy_XCFGI_35(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register57_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xffff;\ +} + +#define _SET_SYSCON_REG_register58_dphy_ctrl0_efuse_in(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3F); \ + _ezchip_macro_read_value_ |= (v&0x3F); \ + MA_OUTW(isp_syscontroller_register58_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register58_dphy_ctrl0_efuse_in(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x3f;\ +} + +#define _SET_SYSCON_REG_register58_dphy_ctrl0_efuse_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<8); \ + _ezchip_macro_read_value_ |= (v&0x1)<<8; \ + MA_OUTW(isp_syscontroller_register58_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register58_dphy_ctrl0_efuse_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR) >> 8; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register58_dphy_ctrl1_efuse_in(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3F<<16); \ + _ezchip_macro_read_value_ |= (v&0x3F)<<16; \ + MA_OUTW(isp_syscontroller_register58_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register58_dphy_ctrl1_efuse_in(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0x3f;\ +} + +#define _SET_SYSCON_REG_register58_dphy_ctrl1_efuse_en(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1<<24); \ + _ezchip_macro_read_value_ |= (v&0x1)<<24; \ + MA_OUTW(isp_syscontroller_register58_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register58_dphy_ctrl1_efuse_en(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register58_REG_ADDR) >> 24; \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register59_dphy_data_bus16_8(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register59_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x1); \ + _ezchip_macro_read_value_ |= (v&0x1); \ + MA_OUTW(isp_syscontroller_register59_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register59_dphy_data_bus16_8(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register59_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0x1;\ +} + +#define _SET_SYSCON_REG_register59_dphy_pll_clk_sel(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register59_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0x3FF<<16); \ + _ezchip_macro_read_value_ |= (v&0x3FF)<<16; \ + MA_OUTW(isp_syscontroller_register59_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register59_dphy_pll_clk_sel(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register59_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0x3ff;\ +} + +#define _SET_SYSCON_REG_register60_dphy_precounter_in_clk(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register60_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF); \ + _ezchip_macro_read_value_ |= (v&0xFF); \ + MA_OUTW(isp_syscontroller_register60_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register60_dphy_precounter_in_clk(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register60_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#define _SET_SYSCON_REG_register60_dphy_precounter_in_clk1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register60_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF<<8); \ + _ezchip_macro_read_value_ |= (v&0xFF)<<8; \ + MA_OUTW(isp_syscontroller_register60_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register60_dphy_precounter_in_clk1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register60_REG_ADDR) >> 8; \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#define _SET_SYSCON_REG_register61_dphy_precounter_in_lan0(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF); \ + _ezchip_macro_read_value_ |= (v&0xFF); \ + MA_OUTW(isp_syscontroller_register61_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register61_dphy_precounter_in_lan0(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR); \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#define _SET_SYSCON_REG_register61_dphy_precounter_in_lan1(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF<<8); \ + _ezchip_macro_read_value_ |= (v&0xFF)<<8; \ + MA_OUTW(isp_syscontroller_register61_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register61_dphy_precounter_in_lan1(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR) >> 8; \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#define _SET_SYSCON_REG_register61_dphy_precounter_in_lan2(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF<<16); \ + _ezchip_macro_read_value_ |= (v&0xFF)<<16; \ + MA_OUTW(isp_syscontroller_register61_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register61_dphy_precounter_in_lan2(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR) >> 16; \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#define _SET_SYSCON_REG_register61_dphy_precounter_in_lan3(v) { \ + uint32_t _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR); \ + _ezchip_macro_read_value_ &= ~(0xFF<<24); \ + _ezchip_macro_read_value_ |= (v&0xFF)<<24; \ + MA_OUTW(isp_syscontroller_register61_REG_ADDR,_ezchip_macro_read_value_); \ +} + +#define _GET_SYSCON_REG_register61_dphy_precounter_in_lan3(_ezchip_macro_read_value_) { \ + _ezchip_macro_read_value_=MA_INW(isp_syscontroller_register61_REG_ADDR) >> 24; \ + _ezchip_macro_read_value_ &= 0xff;\ +} + +#endif //_ISP_SYSCONTROLLER_MACRO_H_ |