diff options
Diffstat (limited to 'arch/riscv/dts/dubhe80-cpus.dtsi')
| -rw-r--r-- | arch/riscv/dts/dubhe80-cpus.dtsi | 169 |
1 files changed, 169 insertions, 0 deletions
diff --git a/arch/riscv/dts/dubhe80-cpus.dtsi b/arch/riscv/dts/dubhe80-cpus.dtsi new file mode 100644 index 0000000000..5861b48844 --- /dev/null +++ b/arch/riscv/dts/dubhe80-cpus.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x0>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x1>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x2>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x3>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <0x100000>; + cache-unified; + }; + }; +}; |