Revert "Merge tag 'JH7110_515_SDK_v4.3.0' into vf2-devel"

This reverts commit 5d4dcdb90d7350760f065f7ea8d658080ad898a1, reversing
changes made to da9a5b042e5c3bcfa3acd65d434338f5baae34f8.

27 files changed, 4 insertions, 3948 deletions

diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 581d8b62cd..b66ffb12fc 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -696,17 +696,9 @@ static int jh7110_clk_init(struct udevice *dev)
 			"u5_dw_i2c_clk_apb", "apb0",
 			SYS_OFFSET(JH7110_I2C5_CLK_APB)));
 	clk_dm(JH7110_I2C5_CLK_CORE,
-		starfive_clk_fix_factor(priv->sys,
-			"u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
-
-	/*i2c2*/
-	clk_dm(JH7110_I2C2_CLK_APB,
 		starfive_clk_gate(priv->sys,
-			"u2_dw_i2c_clk_apb", "apb0",
-			SYS_OFFSET(JH7110_I2C2_CLK_APB)));
-	clk_dm(JH7110_I2C2_CLK_CORE,
-		starfive_clk_fix_factor(priv->sys,
-			"u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
+			"u5_dw_i2c_clk_core", "osc",
+			SYS_OFFSET(JH7110_I2C5_CLK_CORE)));
 
 	return 0;
 }
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 0b8bbcab03..99b3f9ae71 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -30,13 +30,6 @@ config IMX8M_POWER_DOMAIN
 	  Enable support for manipulating NXP i.MX8M on-SoC power domains via
 	  requests to the ATF.
 
-config STARFIVE_POWER_DOMAIN
-	bool "Enable starfive power domain driver"
-	depends on POWER_DOMAIN
-	help
-	  Enable support for pwoer up on-SoC power domains via
-	  requests to the ATF.
-
 config MTK_POWER_DOMAIN
 	bool "Enable the MediaTek power domain driver"
 	depends on POWER_DOMAIN && ARCH_MEDIATEK
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 9e7cdc5fa0..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -15,4 +15,3 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
 obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
-obj-$(CONFIG_STARFIVE_POWER_DOMAIN) += starfive-power-domain.o
diff --git a/drivers/power/domain/starfive-power-domain.c b/drivers/power/domain/starfive-power-domain.c
deleted file mode 100644
index d33c9a5c46..0000000000
--- a/drivers/power/domain/starfive-power-domain.c
+++ /dev/null
@@ -1,155 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-#include <asm/io.h>
-#include <common.h>
-#include <dm.h>
-#include <linux/bitops.h>
-#include <linux/iopoll.h>
-#include <malloc.h>
-#include <power-domain-uclass.h>
-
-#define usleep_range(a, b) udelay((b))
-
-#define MAX_DOMAINS	64
-#define TIMEOUT_US		100000
-
-/* register define */
-#define HW_EVENT_TURN_ON_MASK		0x04
-#define HW_EVENT_TURN_OFF_MASK		0x08
-#define SW_TURN_ON_POWER_MODE		0x0C
-#define SW_TURN_OFF_POWER_MODE		0x10
-#define SW_ENCOURAGE			0x44
-#define PMU_INT_MASK			0x48
-#define PCH_BYPASS			0x4C
-#define PCH_PSTATE			0x50
-#define PCH_TIMEOUT			0x54
-#define LP_TIMEOUT			0x58
-#define HW_TURN_ON_MODE			0x5C
-#define CURR_POWER_MODE			0x80
-#define PMU_EVENT_STATUS		0x88
-#define PMU_INT_STATUS			0x8C
-
-/* sw encourage cfg */
-#define SW_MODE_ENCOURAGE_EN_LO		0x05
-#define SW_MODE_ENCOURAGE_EN_HI		0x50
-#define SW_MODE_ENCOURAGE_DIS_LO	0x0A
-#define SW_MODE_ENCOURAGE_DIS_HI	0xA0
-#define SW_MODE_ENCOURAGE_ON		0xFF
-
-struct sf_power_domain {
-	void __iomem *regs;
-};
-
-static int sf_power_domain_request(struct power_domain *power_domain)
-{
-	if (power_domain->id >= MAX_DOMAINS)
-		return -EINVAL;
-
-	return 0;
-}
-
-static int sf_power_domain_free(struct power_domain *power_domain)
-{
-	return 0;
-}
-
-static int sf_power_domain_on(struct power_domain *power_domain)
-{
-	struct sf_power_domain *priv = dev_get_priv(power_domain->dev);
-	uint32_t mode;
-	uint32_t val;
-	uint32_t encourage_lo;
-	uint32_t encourage_hi;
-	int ret;
-	mode = SW_TURN_ON_POWER_MODE;
-	encourage_lo = SW_MODE_ENCOURAGE_EN_LO;
-	encourage_hi = SW_MODE_ENCOURAGE_EN_HI;
-
-	/* write SW_ENCOURAGE to make the configuration take effect */
-	val = __raw_readl(priv->regs + mode) | BIT(power_domain->id);
-
-	__raw_writel(val, priv->regs + mode);
-	__raw_writel(SW_MODE_ENCOURAGE_ON, priv->regs + SW_ENCOURAGE);
-	__raw_writel(encourage_lo, priv->regs + SW_ENCOURAGE);
-	__raw_writel(encourage_hi, priv->regs + SW_ENCOURAGE);
-
-	ret = readl_poll_timeout(priv->regs + CURR_POWER_MODE, val,
-					val & BIT(power_domain->id),
-					TIMEOUT_US);
-	if (ret) {
-		pr_err("power_on failed");
-		return -ETIMEDOUT;
-	}
-
-
-	return 0;
-}
-
-static int sf_power_domain_off(struct power_domain *power_domain)
-{
-	struct sf_power_domain *priv = dev_get_priv(power_domain->dev);
-	uint32_t mode;
-	uint32_t val;
-	uint32_t encourage_lo;
-	uint32_t encourage_hi;
-	int ret;
-	mode = SW_TURN_OFF_POWER_MODE;
-	encourage_lo = SW_MODE_ENCOURAGE_DIS_LO;
-	encourage_hi = SW_MODE_ENCOURAGE_DIS_HI;
-
-	val = __raw_readl(priv->regs + mode) & ~(BIT(power_domain->id));
-
-	__raw_writel(val, priv->regs + mode);
-	__raw_writel(SW_MODE_ENCOURAGE_ON, priv->regs + SW_ENCOURAGE);
-	__raw_writel(encourage_lo, priv->regs + SW_ENCOURAGE);
-	__raw_writel(encourage_hi, priv->regs + SW_ENCOURAGE);
-
-	ret = readl_poll_timeout(priv->regs + CURR_POWER_MODE, val,
-					!(val & BIT(power_domain->id)),
-					TIMEOUT_US);
-	if (ret) {
-		pr_err("power_off failed");
-		return -ETIMEDOUT;
-	}
-
-
-	return 0;
-}
-
-
-static int sf_power_domain_probe(struct udevice *dev)
-{
-	struct sf_power_domain *priv = dev_get_priv(dev);
-
-	fdt_addr_t addr;
-	addr = dev_read_addr_index(dev, 0);
-	priv->regs = (void __iomem *)addr;
-
-	if (!priv->regs)
-		return -EINVAL;
-
-	return 0;
-}
-
-static const struct udevice_id sf_power_domain_ids[] = {
-	{ .compatible = "starfive,jh7110-pmu" },
-	{ /* sentinel */ }
-};
-
-struct power_domain_ops sf_power_domain_ops = {
-	.rfree = sf_power_domain_free,
-	.off = sf_power_domain_off,
-	.on = sf_power_domain_on,
-	.request = sf_power_domain_request,
-};
-
-U_BOOT_DRIVER(sf_power_domain) = {
-	.name = "sf_power_domain",
-	.id = UCLASS_POWER_DOMAIN,
-	.of_match = sf_power_domain_ids,
-	.ops = &sf_power_domain_ops,
-	.priv_auto	= sizeof(struct sf_power_domain),
-	.probe = sf_power_domain_probe,
-};
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 693576d0a8..fd6648b313 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -342,10 +342,3 @@ config PMIC_TPS65941
 	help
 	The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
 	This driver binds the pmic children.
-
-config PMIC_STARFIVE
-	bool "Enable driver for STARFIVE PMIC"
-	depends on DM_PMIC
-	help
-	The PMIC contains a bunch of SMPS & LDOs.
-	This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f447328201..5d1a97e5f6 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -42,4 +42,3 @@ obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
 obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
 obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
 obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
-obj-$(CONFIG_PMIC_STARFIVE) += pmic_starfive.o
diff --git a/drivers/power/pmic/pmic_starfive.c b/drivers/power/pmic/pmic_starfive.c
deleted file mode 100644
index 71e4d2c519..0000000000
--- a/drivers/power/pmic/pmic_starfive.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2023 Starfive, Inc.
- * Author:	keith.zhao<keith.zhao@statfivetech.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <errno.h>
-#include <dm.h>
-#include <i2c.h>
-#include <log.h>
-#include <power/pmic.h>
-#include <power/regulator.h>
-#include <dm/device.h>
-
-#define	LP8732		0x0
-#define LP8733		0x1
-
-#define LP873X_LDO_NUM		8
-
-/* Drivers name */
-#define LP873X_LDO_DRIVER	"lp873x_ldo"
-#define LP873X_BUCK_DRIVER	"lp873x_buck"
-
-#define LP873X_BUCK_VOLT_MASK		0xFF
-#define LP873X_BUCK_VOLT_MAX_HEX	0xFF
-#define LP873X_BUCK_VOLT_MAX		3360000
-#define LP873X_BUCK_MODE_MASK		0x1
-
-#define LP873X_LDO_VOLT_MASK    0x1F
-#define LP873X_LDO_VOLT_MAX_HEX 0x19
-#define LP873X_LDO_VOLT_MAX     3300000
-#define LP873X_LDO_MODE_MASK	0x1
-
-static const struct pmic_child_info pmic_children_info[] = {
-	{ .prefix = "ldo", .driver = LP873X_LDO_DRIVER },
-	{ },
-};
-
-static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff,
-			  int len)
-{
-	if (dm_i2c_write(dev, reg, buff, len)) {
-		pr_err("write error to device: %p register: %#x!\n", dev, reg);
-		return -EIO;
-	}
-
-	return 0;
-}
-
-static int lp873x_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
-{
-	if (dm_i2c_read(dev, reg, buff, len)) {
-		pr_err("read error from device: %p register: %#x!\n", dev, reg);
-		return -EIO;
-	}
-
-	return 0;
-}
-
-static int starfive_bind(struct udevice *dev)
-{
-	ofnode regulators_node;
-	int children;
-
-	regulators_node = dev_read_subnode(dev, "regulators");
-	if (!ofnode_valid(regulators_node)) {
-		printf("%s: %s regulators subnode not found!\n", __func__,
-		      dev->name);
-		return -ENXIO;
-	}
-
-	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
-	if (!children)
-		printf("%s: %s - no child found\n", __func__, dev->name);
-
-	/* Always return success for this device */
-	return 0;
-}
-
-static struct dm_pmic_ops lp873x_ops = {
-	.read = lp873x_read,
-	.write = lp873x_write,
-};
-
-static const struct udevice_id starfive_ids[] = {
-	{ .compatible = "starfive,jh7110-evb-regulator", .data = LP8732 },
-	{ }
-};
-
-U_BOOT_DRIVER(pmic_starfive) = {
-	.name = "pmic_starfive",
-	.id = UCLASS_PMIC,
-	.of_match = starfive_ids,
-	.bind = starfive_bind,
-	.ops = &lp873x_ops,
-};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index fc5b1062f4..cd253b95f2 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -266,14 +266,6 @@ config DM_REGULATOR_LP873X
 	features for REGULATOR LP873X and the family of LP873X PMICs.
 	The driver implements get/set api for: value and enable.
 
-config DM_REGULATOR_STARFIVE
-	bool "Enable driver for STARFIVE PMIC regulators"
-        depends on PMIC_STARFIVE
-	---help---
-	This enables implementation of driver-model regulator uclass
-	features for REGULATOR LP873X and the family of LP873X PMICs.
-	The driver implements get/set api for: value and enable.
-
 config DM_REGULATOR_LP87565
 	bool "Enable driver for LP87565 PMIC regulators"
         depends on PMIC_LP87565
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index b3085c6a1a..677134c822 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
-obj-$(CONFIG_$(SPL_)DM_REGULATOR_STARFIVE) += starfive_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
 obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
diff --git a/drivers/power/regulator/starfive_regulator.c b/drivers/power/regulator/starfive_regulator.c
deleted file mode 100644
index 548accd5b1..0000000000
--- a/drivers/power/regulator/starfive_regulator.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2023 Starfive, Inc.
- * Author:	keith.zhao<keith.zhao@statfivetech.com>
- */
-
-
-#include <common.h>
-#include <fdtdec.h>
-#include <errno.h>
-#include <dm.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <power/regulator.h>
-#include <power/lp873x.h>
-
-static const char lp873x_ldo_ctrl[LP873X_LDO_NUM] = {0x8, 0x9};
-static const char lp873x_ldo_volt[LP873X_LDO_NUM] = {0xA, 0xB};
-
-
-static int lp873x_ldo_enable(struct udevice *dev, int op, bool *enable)
-{
-	int ret;
-	unsigned int adr;
-	struct dm_regulator_uclass_plat *uc_pdata;
-
-	uc_pdata = dev_get_uclass_plat(dev);
-	adr = uc_pdata->ctrl_reg;
-
-	ret = pmic_reg_read(dev->parent, adr);
-	if (ret < 0)
-		return ret;
-
-	if (op == PMIC_OP_GET) {
-		ret &= LP873X_LDO_MODE_MASK;
-
-		if (ret)
-			*enable = true;
-		else
-			*enable = false;
-
-		return 0;
-	} else if (op == PMIC_OP_SET) {
-		if (*enable)
-			ret |= LP873X_LDO_MODE_MASK;
-		else
-			ret &= ~(LP873X_LDO_MODE_MASK);
-
-		ret = pmic_reg_write(dev->parent, adr, ret);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int lp873x_ldo_volt2hex(int uV)
-{
-	if (uV > LP873X_LDO_VOLT_MAX)
-		return -EINVAL;
-
-	return (uV - 800000) / 100000;
-}
-
-static int lp873x_ldo_hex2volt(int hex)
-{
-	if (hex > LP873X_LDO_VOLT_MAX_HEX)
-		return -EINVAL;
-
-	if (!hex)
-		return 0;
-
-	return (hex * 100000) + 800000;
-}
-
-static int lp873x_ldo_val(struct udevice *dev, int op, int *uV)
-{
-	unsigned int hex, adr;
-	int ret;
-
-	struct dm_regulator_uclass_plat *uc_pdata;
-
-	if (op == PMIC_OP_GET)
-		*uV = 0;
-
-	uc_pdata = dev_get_uclass_plat(dev);
-
-	adr = uc_pdata->volt_reg;
-
-	ret = pmic_reg_read(dev->parent, adr);
-	if (ret < 0)
-		return ret;
-
-	if (op == PMIC_OP_GET) {
-		ret &= LP873X_LDO_VOLT_MASK;
-		ret = lp873x_ldo_hex2volt(ret);
-		if (ret < 0)
-			return ret;
-		*uV = ret;
-		return 0;
-	}
-
-	hex = lp873x_ldo_volt2hex(*uV);
-	if (hex < 0)
-		return hex;
-
-	ret &= ~LP873X_LDO_VOLT_MASK;
-	ret |= hex;
-	if (*uV > 1650000)
-		ret |= 0x80;
-	ret = pmic_reg_write(dev->parent, adr, ret);
-
-	return ret;
-}
-
-static int lp873x_ldo_probe(struct udevice *dev)
-{
-	struct dm_regulator_uclass_plat *uc_pdata;
-
-	uc_pdata = dev_get_uclass_plat(dev);
-	uc_pdata->type = REGULATOR_TYPE_LDO;
-
-	int idx = dev->driver_data;
-	if (idx >= LP873X_LDO_NUM) {
-		return -1;
-	}
-
-	uc_pdata->ctrl_reg = lp873x_ldo_ctrl[idx];
-	uc_pdata->volt_reg = lp873x_ldo_volt[idx];
-
-	return 0;
-}
-
-static int ldo_get_value(struct udevice *dev)
-{
-	int uV;
-	int ret;
-
-	ret = lp873x_ldo_val(dev, PMIC_OP_GET, &uV);
-	if (ret)
-		return ret;
-
-	return uV;
-}
-
-static int ldo_set_value(struct udevice *dev, int uV)
-{
-	return lp873x_ldo_val(dev, PMIC_OP_SET, &uV);
-}
-
-static int ldo_get_enable(struct udevice *dev)
-{
-	bool enable = false;
-	int ret;
-
-	ret = lp873x_ldo_enable(dev, PMIC_OP_GET, &enable);
-	if (ret)
-		return ret;
-
-	return enable;
-}
-
-static int ldo_set_enable(struct udevice *dev, bool enable)
-{
-	return lp873x_ldo_enable(dev, PMIC_OP_SET, &enable);
-}
-
-static const struct dm_regulator_ops lp873x_ldo_ops = {
-	.get_value  = ldo_get_value,
-	.set_value  = ldo_set_value,
-	.get_enable = ldo_get_enable,
-	.set_enable = ldo_set_enable,
-};
-
-U_BOOT_DRIVER(lp873x_ldo) = {
-	.name = LP873X_LDO_DRIVER,
-	.id = UCLASS_REGULATOR,
-	.ops = &lp873x_ldo_ops,
-	.probe = lp873x_ldo_probe,
-};
-
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 41d11e5daa..8b940d70eb 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -430,15 +430,6 @@ config VIDEO_LCD_RAYDIUM_RM68200
 	Say Y here if you want to enable support for Raydium RM68200
 	720x1280 DSI video mode panel.
 
-config VIDEO_LCD_STARFIVE_SEEED
-	bool "seeed DSI LCD panel support"
-	depends on DM_VIDEO
-	select VIDEO_MIPI_DSI
-	default n
-	help
-	Say Y here if you want to enable support for seeed
-	800X480 DSI video mode panel.
-
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	default n
@@ -1022,6 +1013,4 @@ config VIDEO_VCXK
 	  This enables VCXK driver which can be used with VC2K, VC4K
 	  and VC8K devices on various boards from BuS Elektronik GmbH.
 
-source "drivers/video/starfive/Kconfig"
-
 endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index e84280a04f..7ae0ab2b35 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -23,7 +23,6 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 obj-${CONFIG_VIDEO_STM32} += stm32/
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-${CONFIG_VIDEO_STARFIVE} += starfive/
 obj-y += ti/
 
 obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
@@ -57,7 +56,6 @@ obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
-obj-$(CONFIG_VIDEO_LCD_STARFIVE_SEEED) += raydium-rm68200-starfive.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
 obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
diff --git a/drivers/video/raydium-rm68200-starfive.c b/drivers/video/raydium-rm68200-starfive.c
deleted file mode 100644
index d455e5946d..0000000000
--- a/drivers/video/raydium-rm68200-starfive.c
+++ /dev/null
@@ -1,340 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
- * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
- *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
- *
- * This rm68200 panel driver is inspired from the Linux Kernel driver
- * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
- */
-#include <common.h>
-#include <backlight.h>
-#include <dm.h>
-#include <mipi_dsi.h>
-#include <panel.h>
-#include <asm/gpio.h>
-#include <dm/device_compat.h>
-#include <linux/delay.h>
-#include <power/regulator.h>
-#include <i2c.h>
-
-/* I2C registers of the Atmel microcontroller. */
-enum REG_ADDR {
-	REG_ID = 0x80,
-	REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
-	REG_PORTB,
-	REG_PORTC,
-	REG_PORTD,
-	REG_POWERON,
-	REG_PWM,
-	REG_DDRA,
-	REG_DDRB,
-	REG_DDRC,
-	REG_DDRD,
-	REG_TEST,
-	REG_WR_ADDRL,
-	REG_WR_ADDRH,
-	REG_READH,
-	REG_READL,
-	REG_WRITEH,
-	REG_WRITEL,
-	REG_ID2,
-};
-
-/* DSI D-PHY Layer Registers */
-#define D0W_DPHYCONTTX 0x0004
-#define CLW_DPHYCONTRX 0x0020
-#define D0W_DPHYCONTRX 0x0024
-#define D1W_DPHYCONTRX 0x0028
-#define COM_DPHYCONTRX 0x0038
-#define CLW_CNTRL 0x0040
-#define D0W_CNTRL 0x0044
-#define D1W_CNTRL 0x0048
-#define DFTMODE_CNTRL 0x0054
-
-/* DSI PPI Layer Registers */
-#define PPI_STARTPPI 0x0104
-#define PPI_BUSYPPI 0x0108
-#define PPI_LINEINITCNT 0x0110
-#define PPI_LPTXTIMECNT 0x0114
-#define PPI_CLS_ATMR 0x0140
-#define PPI_D0S_ATMR 0x0144
-#define PPI_D1S_ATMR 0x0148
-#define PPI_D0S_CLRSIPOCOUNT 0x0164
-#define PPI_D1S_CLRSIPOCOUNT 0x0168
-#define CLS_PRE 0x0180
-#define D0S_PRE 0x0184
-#define D1S_PRE 0x0188
-#define CLS_PREP 0x01A0
-#define D0S_PREP 0x01A4
-#define D1S_PREP 0x01A8
-#define CLS_ZERO 0x01C0
-#define D0S_ZERO 0x01C4
-#define D1S_ZERO 0x01C8
-#define PPI_CLRFLG 0x01E0
-#define PPI_CLRSIPO 0x01E4
-#define HSTIMEOUT 0x01F0
-#define HSTIMEOUTENABLE 0x01F4
-
-/* DSI Protocol Layer Registers */
-#define DSI_STARTDSI 0x0204
-#define DSI_BUSYDSI 0x0208
-#define DSI_LANEENABLE 0x0210
-#define DSI_LANEENABLE_CLOCK BIT(0)
-#define DSI_LANEENABLE_D0 BIT(1)
-#define DSI_LANEENABLE_D1 BIT(2)
-
-#define DSI_LANESTATUS0 0x0214
-#define DSI_LANESTATUS1 0x0218
-#define DSI_INTSTATUS 0x0220
-#define DSI_INTMASK 0x0224
-#define DSI_INTCLR 0x0228
-#define DSI_LPTXTO 0x0230
-#define DSI_MODE 0x0260
-#define DSI_PAYLOAD0 0x0268
-#define DSI_PAYLOAD1 0x026C
-#define DSI_SHORTPKTDAT 0x0270
-#define DSI_SHORTPKTREQ 0x0274
-#define DSI_BTASTA 0x0278
-#define DSI_BTACLR 0x027C
-
-/* DSI General Registers */
-#define DSIERRCNT 0x0300
-#define DSISIGMOD 0x0304
-
-/* DSI Application Layer Registers */
-#define APLCTRL 0x0400
-#define APLSTAT 0x0404
-#define APLERR 0x0408
-#define PWRMOD 0x040C
-#define RDPKTLN 0x0410
-#define PXLFMT 0x0414
-#define MEMWRCMD 0x0418
-
-/* LCDC/DPI Host Registers */
-#define LCDCTRL 0x0420
-#define HSR 0x0424
-#define HDISPR 0x0428
-#define VSR 0x042C
-#define VDISPR 0x0430
-#define VFUEN 0x0434
-
-/* DBI-B Host Registers */
-#define DBIBCTRL 0x0440
-
-/* SPI Master Registers */
-#define SPICMR 0x0450
-#define SPITCR 0x0454
-
-/* System Controller Registers */
-#define SYSSTAT 0x0460
-#define SYSCTRL 0x0464
-#define SYSPLL1 0x0468
-#define SYSPLL2 0x046C
-#define SYSPLL3 0x0470
-#define SYSPMCTRL 0x047C
-
-/* GPIO Registers */
-#define GPIOC 0x0480
-#define GPIOO 0x0484
-#define GPIOI 0x0488
-
-/* I2C Registers */
-#define I2CCLKCTRL 0x0490
-
-/* Chip/Rev Registers */
-#define IDREG 0x04A0
-
-/* Debug Registers */
-#define WCMDQUEUE 0x0500
-#define RCMDQUEUE 0x0504
-
-
-struct rm68200_panel_priv {
-	struct udevice *reg;
-	struct udevice *backlight;
-	struct gpio_desc reset;
-};
-
-static const struct display_timing default_timing = {
-	.pixelclock.typ		= 29700000,
-	.hactive.typ		= 800,
-	.hfront_porch.typ	= 90,
-	.hback_porch.typ	= 5,
-	.hsync_len.typ		= 5,
-	.vactive.typ		= 480,
-	.vfront_porch.typ	= 60,
-	.vback_porch.typ	= 5,
-	.vsync_len.typ		= 5,
-};
-
-static int seeed_panel_i2c_write(struct udevice *dev, uint addr, uint mask, uint data)
-{
-	uint8_t valb;
-	int err = 0;
-
-	if (mask != 0xff){
-		err = dm_i2c_read(dev, addr, &valb, 1);
-		if (err)
-			return err;
-	}
-	valb &= ~mask;
-	valb |= data;
-
-	err = dm_i2c_write(dev, addr, &valb, 1);
-	return err;
-}
-
-static int seeed_panel_i2c_read(struct udevice *dev, uint8_t addr, uint8_t *data)
-{
-	uint8_t valb;
-	int err;
-
-	err = dm_i2c_read(dev, addr, &valb, 1);
-	if (err)
-		return err;
-
-	*data = (int)valb;
-	return 0;
-}
-
-static void rpi_touchscreen_write(struct udevice *dev, u16 reg, u32 val)
-{
-	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
-	struct mipi_dsi_device *device = plat->device;
-	int err;
-
-    u8 msg[] = {
-        reg,
-        reg >> 8,
-        val,
-        val >> 8,
-        val >> 16,
-        val >> 24,
-    };
-
-	err = mipi_dsi_dcs_write_buffer(device, msg, sizeof(msg));
-	if (err < 0)
-		dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
-
-    return;
-}
-
-static int rm68200_panel_enable_backlight(struct udevice *dev)
-{
-	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
-	struct mipi_dsi_device *device = plat->device;
-	int ret;
-	int i;
-	u8 reg_value = 0;
-
-	ret = mipi_dsi_attach(device);
-	if (ret < 0)
-		return ret;
-
-	seeed_panel_i2c_write(dev, REG_POWERON, 0xff, 1);
-
-	mdelay(100);
-	/* Wait for nPWRDWN to go low to indicate poweron is done. */
-	for (i = 0; i < 100; i++) {
-		seeed_panel_i2c_read(dev, REG_PORTB, &reg_value);
-		if (reg_value & 1)
-			break;
-	}
-
-	rpi_touchscreen_write(dev, DSI_LANEENABLE,
-				DSI_LANEENABLE_CLOCK |
-				DSI_LANEENABLE_D0);
-
-	rpi_touchscreen_write(dev,PPI_D0S_CLRSIPOCOUNT, 0x05);
-	rpi_touchscreen_write(dev,PPI_D1S_CLRSIPOCOUNT, 0x05);
-	rpi_touchscreen_write(dev,PPI_D0S_ATMR, 0x00);
-	rpi_touchscreen_write(dev,PPI_D1S_ATMR, 0x00);
-	rpi_touchscreen_write(dev,PPI_LPTXTIMECNT, 0x03);
-
-	rpi_touchscreen_write(dev,SPICMR, 0x00);
-	rpi_touchscreen_write(dev,LCDCTRL, 0x00100150);
-	rpi_touchscreen_write(dev,SYSCTRL, 0x040f);
-	mdelay(100);
-
-	rpi_touchscreen_write(dev,PPI_STARTPPI, 0x01);
-	rpi_touchscreen_write(dev,DSI_STARTDSI, 0x01);
-	mdelay(100);
-
-	/* Turn on the backlight. */
-	seeed_panel_i2c_write(dev,REG_PWM,	255, 255);
-	mdelay(100);
-
-	/* Default to the same orientation as the closed source
-	* firmware used for the panel.  Runtime rotation
-	* configuration will be supported using VC4's plane
-	* orientation bits.
-	*/
-	seeed_panel_i2c_write(dev,REG_PORTA,255, BIT(2));
-	mdelay(100);
-
-
-	return 0;
-}
-
-static int rm68200_panel_get_display_timing(struct udevice *dev,
-					    struct display_timing *timings)
-{
-	memcpy(timings, &default_timing, sizeof(*timings));
-	return 0;
-}
-
-static int rm68200_panel_of_to_plat(struct udevice *dev)
-{
-	return 0;
-}
-
-static int rm68200_panel_probe(struct udevice *dev)
-{
-	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
-
-	u8 reg_value = 0;
-
-	/* fill characteristics of DSI data link */
-	plat->lanes = 1;
-	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO |
-			   MIPI_DSI_MODE_VIDEO_BURST |
-			   MIPI_DSI_MODE_LPM;
-
-	seeed_panel_i2c_read(dev, 0x80, &reg_value);
-
-	debug("%s,reg_value = %d\n", __func__,reg_value);
-	switch (reg_value) {
-	   case 0xde: /* ver 1 */
-	   case 0xc3: /* ver 2 */
-	   break;
-
-	   default:
-		   printf("Unknown Atmel firmware revision: 0x%02x\n", reg_value);
-		   return -ENODEV;
-	}
-
-	return 0;
-}
-
-static const struct panel_ops rm68200_panel_ops = {
-	.enable_backlight = rm68200_panel_enable_backlight,
-	.get_display_timing = rm68200_panel_get_display_timing,
-};
-
-static const struct udevice_id rm68200_panel_ids[] = {
-	{ .compatible = "raydium,rm68200" },
-	{ }
-};
-
-U_BOOT_DRIVER(rm68200_panel) = {
-	.name			  = "rm68200_panel",
-	.id			  = UCLASS_PANEL,
-	.of_match		  = rm68200_panel_ids,
-	.ops			  = &rm68200_panel_ops,
-	.of_to_plat	  = rm68200_panel_of_to_plat,
-	.probe			  = rm68200_panel_probe,
-	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
-	.priv_auto	= sizeof(struct rm68200_panel_priv),
-};
diff --git a/drivers/video/starfive/Kconfig b/drivers/video/starfive/Kconfig
deleted file mode 100644
index ce6e2cefc1..0000000000
--- a/drivers/video/starfive/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-#
-# Video drivers selection for rockchip soc. These configs only impact the
-# compile process. You can surely check all the options. In this case, all the
-# display driver will be compiled, but which drivers finally  will be used is
-# decided by device tree configuration. What's more, enable needed power for
-# display by configure the device tree, and the vop driver will do the rest.
-#
-# Author: Eric Gao <eric.gao@rock-chips.com>
-#
-
-menuconfig VIDEO_STARFIVE
-	bool "Enable STARFIVE Video Support"
-	depends on DM_VIDEO
-	help
-	  STARFIVE SoCs provide video output capabilities for High-Definition
-	  Multimedia Interface (HDMI), Low-voltage Differential Signalling
-	  (LVDS), embedded DisplayPort (eDP) and Display Serial Interface (DSI).
-
-	  This driver supports the on-chip video output device, and targets the
-	  STARFIVE RK3288 and RK3399.
-
-config VIDEO_STARFIVE_MAX_XRES
-        int "Maximum horizontal resolution (for memory allocation purposes)"
-	depends on VIDEO_STARFIVE
-	default 3840 if DISPLAY_STARFIVE_HDMI
-	default 1920
-	help
-	  The maximum horizontal resolution to support for the framebuffer.
-	  This configuration is used for reserving/allocating memory for the
-	  framebuffer during device-model binding/probing.
-
-config VIDEO_STARFIVE_MAX_YRES
-        int "Maximum vertical resolution (for memory allocation purposes)"
-	depends on VIDEO_STARFIVE
-	default 2160 if DISPLAY_STARFIVE_HDMI
-	default 1080
-	help
-	  The maximum vertical resolution to support for the framebuffer.
-	  This configuration is used for reserving/allocating memory for the
-	  framebuffer during device-model binding/probing.
-
-if VIDEO_STARFIVE
-
-config DISPLAY_STARFIVE_EDP
-	bool "EDP Port"
-	depends on VIDEO_STARFIVE
-	help
-	  This enables Embedded DisplayPort(EDP) display support.
-
-config DISPLAY_STARFIVE_LVDS
-	bool "LVDS Port"
-	depends on VIDEO_STARFIVE
-	help
-	  This enables Low-voltage Differential Signaling(LVDS) display
-	  support.
-
-config DISPLAY_STARFIVE_HDMI
-	bool "HDMI port"
-	select VIDEO_DW_HDMI
-	depends on VIDEO_STARFIVE
-	help
-	  This enables High-Definition Multimedia Interface display support.
-
-config DISPLAY_STARFIVE_MIPI
-	bool "MIPI Port"
-	depends on VIDEO_STARFIVE
-	help
-	  This enables Mobile Industry Processor Interface(MIPI) display
-	  support. The mipi controller and dphy on rk3288& rk3399 support
-	  16,18, 24 bits per pixel with up to 2k resolution ratio.
-
-config VIDEO_NW_MIPI_DSI
-	bool "DSI host"
-	select VIDEO_MIPI_DSI
-	help
-	  Enables the common driver code for the Northwest
-	  MIPI DSI block found in SoCs from various vendors.
-	  As this does not provide any functionality by itself (but
-	  rather requires a SoC-specific glue driver to call it), it
-	  can not be enabled from the configuration menu.
-endif
diff --git a/drivers/video/starfive/Makefile b/drivers/video/starfive/Makefile
deleted file mode 100644
index d0bb298a94..0000000000
--- a/drivers/video/starfive/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifdef CONFIG_VIDEO_STARFIVE
-obj-y += sf_vop.o
-obj-$(CONFIG_DISPLAY_STARFIVE_EDP) += sf_edp.o
-obj-$(CONFIG_DISPLAY_STARFIVE_LVDS) += sf_lvds.o
-obj-$(CONFIG_DISPLAY_STARFIVE_HDMI) += sf_hdmi.o
-obj-$(CONFIG_DISPLAY_STARFIVE_MIPI) += sf_mipi.o
-obj-$(CONFIG_VIDEO_NW_MIPI_DSI) += mipi_dsi_host.o
-endif
diff --git a/drivers/video/starfive/mipi_dsi_host.c b/drivers/video/starfive/mipi_dsi_host.c
deleted file mode 100644
index 2736eb329f..0000000000
--- a/drivers/video/starfive/mipi_dsi_host.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Copyright 2016-2019 NXP
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <div64.h>
-#include <dm.h>
-#include <dm/device-internal.h>
-#include <dsi_host.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <malloc.h>
-#include <panel.h>
-#include <regmap.h>
-#include <syscon.h>
-#include <video_bridge.h>
-
-#include "sf_mipi.h"
-#include "mipi_dsi_northwest_regs.h"
-
-#define MIPI_LCD_SLEEP_MODE_DELAY	(120)
-#define MIPI_FIFO_TIMEOUT		250000 /* 250ms */
-#define	PS2KHZ(ps)	(1000000000UL / (ps))
-#define MSEC_PER_SEC			1000
-
-#define DIV_ROUND_CLOSEST_ULL(x, divisor)(		\
-{							\
-	typeof(divisor) __d = divisor;			\
-	unsigned long long _tmp = (x) + (__d) / 2;	\
-	do_div(_tmp, __d);				\
-	_tmp;						\
-}							\
-)
-
-enum mipi_dsi_mode {
-	DSI_COMMAND_MODE,
-	DSI_VIDEO_MODE
-};
-
-#define DSI_LP_MODE	0
-#define DSI_HS_MODE	1
-
-enum mipi_dsi_payload {
-	DSI_PAYLOAD_CMD,
-	DSI_PAYLOAD_VIDEO,
-};
-
-/*
- * mipi-dsi northwest driver information structure, holds useful data for the driver.
- */
-struct mipi_dsi_northwest_info {
-	void __iomem *dsi_base;
-	void __iomem *phy_base;
-	void __iomem *mmio_base;
-
-	struct mipi_dsi_device *device;
-	struct mipi_dsi_host dsi_host;
-	struct display_timing timings;
-	struct regmap *sim;
-	const struct mipi_dsi_phy_ops *phy_ops;
-
-	uint32_t max_data_lanes;
-	uint32_t max_data_rate;
-	uint32_t pll_ref;
-	bool link_initialized;
-};
-
-static void cdns_dsi_init_link(struct mipi_dsi_northwest_info *mipi_dsi, struct mipi_dsi_device *device)
-{
-	unsigned long  ulpout;
-	u32 val;
-	int i;
-	struct udevice *dev = device->dev;
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-
-	if (mipi_dsi->link_initialized)
-		return;
-
-	val = WAIT_BURST_TIME(0xf);
-	for (i = 1; i < mipi_dsi->max_data_lanes; i++)
-		val |= DATA_LANE_EN(i);
-
-	debug("%s,device->mode_flags = 0x%ld,mipi_dsi->max_data_lanes = %d\n", __func__,device->mode_flags,mipi_dsi->max_data_lanes);
-
-	if (!(device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
-		val |= CLK_CONTINUOUS;
-
-	writel(val, mipi_dsi->dsi_base + MCTL_MAIN_PHY_CTL);
-
-	ulpout = DIV_ROUND_UP(clk_get_rate(&priv->dsi_sys_clk), MSEC_PER_SEC);
-	debug("%s ulpout: 0x%ld\n", __func__, ulpout);
-
-	writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
-		mipi_dsi->dsi_base + MCTL_ULPOUT_TIME);
-
-	writel(LINK_EN, mipi_dsi->dsi_base + MCTL_MAIN_DATA_CTL);
-
-	val = CLK_LANE_EN | PLL_START ; // | PLL_START; unused bit
-	for (i = 0; i < mipi_dsi->max_data_lanes; i++)
-		val |= DATA_LANE_START(i);
-
-	writel(val, mipi_dsi->dsi_base + MCTL_MAIN_EN);
-	udelay(20);
-
-	mipi_dsi->link_initialized = true;
-}
-
-
-static inline struct mipi_dsi_northwest_info *host_to_dsi(struct mipi_dsi_host *host)
-{
-	return container_of(host, struct mipi_dsi_northwest_info, dsi_host);
-}
-
-static int mipi_dsi_northwest_host_attach(struct mipi_dsi_host *host,
-				   struct mipi_dsi_device *device)
-{
-	return 0;
-}
-
-static int wait_for_send_done(struct mipi_dsi_northwest_info *mipi_dsi, unsigned long timeout)
-{
-   uint32_t irq_status;
-   uint32_t ctl;
-
-   do {
-	   irq_status = readl(mipi_dsi->dsi_base + DIRECT_CMD_STS_FLAG);
-	   if (irq_status)
-	   {
-			ctl = readl(mipi_dsi->dsi_base + DIRECT_CMD_STS_CTL);
-			ctl &= ~irq_status;
-			writel(ctl, mipi_dsi->dsi_base + DIRECT_CMD_STS_CTL);
-		    return timeout;
-	   }
-	   udelay(1);
-   } while (--timeout);
-
-   return 0;
-}
-
-static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
-				const struct mipi_dsi_msg *msg)
-{
-	struct mipi_dsi_northwest_info *dsi = host_to_dsi(host);
-	u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0;
-	struct mipi_dsi_packet packet;
-	int ret, i, tx_len, rx_len;
-	struct udevice *dev = dsi->device->dev;
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-
-	cdns_dsi_init_link(dsi, dsi->device);
-
-	ret = mipi_dsi_create_packet(&packet, msg);
-	if (ret)
-	   goto out;
-
-	tx_len = msg->tx_buf ? msg->tx_len : 0;
-	rx_len = msg->rx_buf ? msg->rx_len : 0;
-
-	/* For read operations, the maximum TX len is 2. */
-	if (rx_len && tx_len > 2) {
-		ret = -ENOTSUPP;
-		goto out;
-	}
-
-	/* TX len is limited by the CMD FIFO depth. */
-	if (tx_len > priv->direct_cmd_fifo_depth) {
-		ret = -ENOTSUPP;
-		goto out;
-	}
-
-	/* RX len is limited by the RX FIFO depth. */
-	if (rx_len > priv->rx_fifo_depth) {
-		ret = -ENOTSUPP;
-		goto out;
-	}
-
-	cmd = CMD_SIZE(tx_len) | CMD_VCHAN_ID(msg->channel) |
-		 CMD_DATATYPE(msg->type);
-
-	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
-	   cmd |= CMD_LP_EN;
-
-	if (mipi_dsi_packet_format_is_long(msg->type))
-	   cmd |= CMD_LONG;
-
-	if (rx_len) {
-		cmd |= READ_CMD;
-		wait = READ_COMPLETED_WITH_ERR | READ_COMPLETED;
-		ctl = READ_EN | BTA_EN;
-	} else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
-		cmd |= BTA_REQ;
-		wait = ACK_WITH_ERR_RCVD | ACK_RCVD;
-		ctl = BTA_EN;
-	}
-	udelay(10);
-	writel(readl(dsi->dsi_base + MCTL_MAIN_DATA_CTL) | ctl,
-		  dsi->dsi_base + MCTL_MAIN_DATA_CTL);
-
-	writel(cmd, dsi->dsi_base + DIRECT_CMD_MAIN_SETTINGS);
-
-	for (i = 0; i < tx_len; i += 4) {
-	   const u8 *buf = msg->tx_buf;
-	   int j;
-
-	   val = 0;
-	   for (j = 0; j < 4 && j + i < tx_len; j++)
-		   val |= (u32)buf[i + j] << (8 * j);
-
-	   writel(val, dsi->dsi_base + DIRECT_CMD_WRDATA);
-	}
-
-	/* Clear status flags before sending the command. */
-	writel(wait, dsi->dsi_base + DIRECT_CMD_STS_CLR);
-	writel(wait, dsi->dsi_base + DIRECT_CMD_STS_CTL);
-
-	writel(0, dsi->dsi_base + DIRECT_CMD_SEND);
-
-	ret = wait_for_send_done(dsi, MIPI_FIFO_TIMEOUT);
-	if (!ret) {
-		printf("wait tx done timeout!\n");
-		return -ETIMEDOUT;
-	}
-	udelay(10);
-	sts = readl(dsi->dsi_base + DIRECT_CMD_STS);
-	writel(wait, dsi->dsi_base + DIRECT_CMD_STS_CLR);
-	writel(0, dsi->dsi_base + DIRECT_CMD_STS_CTL);
-
-	writel(readl(dsi->dsi_base + MCTL_MAIN_DATA_CTL) & ~ctl,
-		  dsi->dsi_base + MCTL_MAIN_DATA_CTL);
-
-	/* We did not receive the events we were waiting for. */
-	if (!(sts & wait)) {
-	   ret = -ETIMEDOUT;
-	   goto out;
-	}
-
-	/* 'READ' or 'WRITE with ACK' failed. */
-	if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {
-	   ret = -EIO;
-	   goto out;
-	}
-
-	for (i = 0; i < rx_len; i += 4) {
-	   u8 *buf = msg->rx_buf;
-	   int j;
-
-	   val = readl(dsi->dsi_base + DIRECT_CMD_RDDATA);
-	   for (j = 0; j < 4 && j + i < rx_len; j++)
-		   buf[i + j] = val >> (8 * j);
-	}
-
-	out:
-
-	return ret;
-}
-
-static const struct mipi_dsi_host_ops mipi_dsi_northwest_host_ops = {
-	.attach = mipi_dsi_northwest_host_attach,
-	.transfer = cdns_dsi_transfer,
-};
-
-static int mipi_dsi_northwest_init(struct udevice *dev,
-			    struct mipi_dsi_device *device,
-			    struct display_timing *timings,
-			    unsigned int max_data_lanes,
-			    const struct mipi_dsi_phy_ops *phy_ops)
-{
-	struct mipi_dsi_northwest_info *priv = dev_get_priv(dev);
-
-	if (!phy_ops->init || !phy_ops->get_lane_mbps ||
-	    !phy_ops->post_set_mode)
-		return -5;
-
-	priv->max_data_lanes = max_data_lanes;
-	priv->device = device;
-	priv->dsi_host.ops = &mipi_dsi_northwest_host_ops;
-	device->host = &priv->dsi_host;
-
-	priv->timings = *timings;
-	priv->phy_ops = phy_ops;
-	priv->dsi_base = (void *)dev_read_addr_name(device->dev, "dsi");
-	priv->phy_base = (void *)dev_read_addr_name(device->dev, "phy");
-
-	if ((fdt_addr_t)priv->dsi_base == FDT_ADDR_T_NONE || (fdt_addr_t)priv->phy_base == FDT_ADDR_T_NONE) {
-		printf("dsi dt register address error\n");
-		return -EINVAL;
-	}
-	priv->link_initialized = false;
-
-	return 0;
-}
-
-static int mipi_dsi_enable(struct udevice *dev)
-{
-	struct mipi_dsi_northwest_info *priv = dev_get_priv(dev);
-
-	priv->phy_ops->init(priv->device);
-	priv->phy_ops->post_set_mode(priv->device, MIPI_DSI_MODE_VIDEO);
-	cdns_dsi_init_link(priv, priv->device);
-
-	writel(0x00670067, priv->dsi_base + 0x000000c0);
-	writel(0x00cb0960, priv->dsi_base + 0x000000c4);
-	writel(0x0003b145, priv->dsi_base + 0x000000b4);
-	writel(0x000001e0, priv->dsi_base + 0x000000b8);
-	writel(0x00000a9e, priv->dsi_base + 0x000000d0);
-	writel(0x0a980000, priv->dsi_base + 0x000000f8);
-	writel(0x00000b0f, priv->dsi_base + 0x000000cc);
-	writel(0x7c3c0aae, priv->dsi_base + 0x000000dc);
-	writel(0x0032dcd3, priv->dsi_base + 0x00000014);
-	writel(0x00032dcd, priv->dsi_base + 0x00000018);
-	writel(0x80b8fe00, priv->dsi_base + 0x000000b0);
-	writel(0x00020027, priv->dsi_base + 0x00000004);
-	writel(0x00004018, priv->dsi_base + 0x0000000c);
-
-	return 0;
-}
-
-static int mipi_dsi_northwest_disable(struct udevice *dev)
-{
-	return 0;
-}
-
-struct dsi_host_ops mipi_dsi_northwest_ops = {
-	.init = mipi_dsi_northwest_init,
-	.enable = mipi_dsi_enable,
-	.disable = mipi_dsi_northwest_disable,
-};
-
-static int mipi_dsi_northwest_probe(struct udevice *dev)
-{
-	return 0;
-}
-
-static const struct udevice_id mipi_dsi_northwest_ids[] = {
-	{ .compatible = "starfive,mipi-dsi" },
-	{ }
-};
-
-U_BOOT_DRIVER(mipi_dsi_host) = {
-	.name			= "mipi_dsi_host",
-	.id				= UCLASS_DSI_HOST,
-	.of_match		= mipi_dsi_northwest_ids,
-	.probe			= mipi_dsi_northwest_probe,
-	.remove 		= mipi_dsi_northwest_disable,
-	.ops			= &mipi_dsi_northwest_ops,
-	.priv_auto	= sizeof(struct mipi_dsi_northwest_info),
-};
diff --git a/drivers/video/starfive/mipi_dsi_northwest_regs.h b/drivers/video/starfive/mipi_dsi_northwest_regs.h
deleted file mode 100644
index 6493403a0c..0000000000
--- a/drivers/video/starfive/mipi_dsi_northwest_regs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __MIPI_DSI_NORTHWEST_REGS_H
-#define __MIPI_DSI_NORTHWEST_REGS_H
-
-/* ----------------------------	register offsets --------------------------- */
-
-/* sim */
-#define SIM_SOPT1		0x0
-#define MIPI_ISO_DISABLE	0x8
-
-#define SIM_SOPT1CFG		0x4
-#define DSI_RST_DPI_N		0x80000000
-#define DSI_RST_ESC_N		0x40000000
-#define DSI_RST_BYTE_N		0x20000000
-#define DSI_SD			0x200
-#define DSI_CM			0x100
-#define DSI_PLL_EN		0x80
-
-/* dphy */
-#define DPHY_PD_DPHY			0x300
-#define DPHY_M_PRG_HS_PREPARE		0x304
-#define DPHY_MC_PRG_HS_PREPARE		0x308
-#define DPHY_M_PRG_HS_ZERO		0x30c
-#define DPHY_MC_PRG_HS_ZERO		0x310
-#define DPHY_M_PRG_HS_TRAIL		0x314
-#define DPHY_MC_PRG_HS_TRAIL		0x318
-#define DPHY_PD_PLL			0x31c
-#define DPHY_TST			0x320
-#define DPHY_CN				0x324
-#define DPHY_CM				0x328
-#define DPHY_CO				0x32c
-#define DPHY_LOCK			0x330
-#define DPHY_LOCK_BYP			0x334
-#define DPHY_RTERM_SEL			0x338
-#define DPHY_AUTO_PD_EN			0x33c
-#define DPHY_RXLPRP			0x340
-#define DPHY_RXCDRP			0x344
-
-/* host */
-#define HOST_CFG_NUM_LANES		0x0
-#define HOST_CFG_NONCONTINUOUS_CLK	0x4
-#define HOST_CFG_T_PRE			0x8
-#define HOST_CFG_T_POST			0xc
-#define HOST_CFG_TX_GAP			0x10
-#define HOST_CFG_AUTOINSERT_EOTP	0x14
-#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP	0x18
-#define HOST_CFG_HTX_TO_COUNT		0x1c
-#define HOST_CFG_LRX_H_TO_COUNT		0x20
-#define HOST_CFG_BTA_H_TO_COUNT		0x24
-#define HOST_CFG_TWAKEUP		0x28
-#define HOST_CFG_STATUS_OUT		0x2c
-#define HOST_RX_ERROR_STATUS		0x30
-
-/* dpi */
-#define DPI_PIXEL_PAYLOAD_SIZE		0x200
-#define DPI_PIXEL_FIFO_SEND_LEVEL	0x204
-#define DPI_INTERFACE_COLOR_CODING	0x208
-#define DPI_PIXEL_FORMAT		0x20c
-#define DPI_VSYNC_POLARITY		0x210
-#define DPI_HSYNC_POLARITY		0x214
-#define DPI_VIDEO_MODE			0x218
-#define DPI_HFP				0x21c
-#define DPI_HBP				0x220
-#define DPI_HSA				0x224
-#define DPI_ENABLE_MULT_PKTS		0x228
-#define DPI_VBP				0x22c
-#define DPI_VFP				0x230
-#define DPI_BLLP_MODE			0x234
-#define DPI_USE_NULL_PKT_BLLP		0x238
-#define DPI_VACTIVE			0x23c
-#define DPI_VC				0x240
-
-/* apb pkt */
-#define HOST_TX_PAYLOAD			0x280
-
-#define HOST_PKT_CONTROL		0x284
-#define HOST_PKT_CONTROL_WC(x)		(((x) & 0xffff) << 0)
-#define HOST_PKT_CONTROL_VC(x)		(((x) & 0x3) << 16)
-#define HOST_PKT_CONTROL_DT(x)		(((x) & 0x3f) << 18)
-#define HOST_PKT_CONTROL_HS_SEL(x)	(((x) & 0x1) << 24)
-#define HOST_PKT_CONTROL_BTA_TX(x)	(((x) & 0x1) << 25)
-#define HOST_PKT_CONTROL_BTA_NO_TX(x)	(((x) & 0x1) << 26)
-
-#define HOST_SEND_PACKET		0x288
-#define HOST_PKT_STATUS			0x28c
-#define HOST_PKT_FIFO_WR_LEVEL		0x290
-#define HOST_PKT_FIFO_RD_LEVEL		0x294
-#define HOST_PKT_RX_PAYLOAD		0x298
-
-#define HOST_PKT_RX_PKT_HEADER		0x29c
-#define HOST_PKT_RX_PKT_HEADER_WC(x)	(((x) & 0xffff) << 0)
-#define HOST_PKT_RX_PKT_HEADER_DT(x)	(((x) & 0x3f) << 16)
-#define HOST_PKT_RX_PKT_HEADER_VC(x)	(((x) & 0x3) << 22)
-
-#define HOST_IRQ_STATUS			0x2a0
-#define HOST_IRQ_STATUS_SM_NOT_IDLE			(1 << 0)
-#define HOST_IRQ_STATUS_TX_PKT_DONE			(1 << 1)
-#define HOST_IRQ_STATUS_DPHY_DIRECTION			(1 << 2)
-#define HOST_IRQ_STATUS_TX_FIFO_OVFLW			(1 << 3)
-#define HOST_IRQ_STATUS_TX_FIFO_UDFLW			(1 << 4)
-#define HOST_IRQ_STATUS_RX_FIFO_OVFLW			(1 << 5)
-#define HOST_IRQ_STATUS_RX_FIFO_UDFLW			(1 << 6)
-#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD			(1 << 7)
-#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD	(1 << 8)
-#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT		(1 << 29)
-#define HOST_IRQ_STATUS_LP_RX_TIMEOUT			(1 << 30)
-#define HOST_IRQ_STATUS_HS_TX_TIMEOUT			(1 << 31)
-
-#define HOST_IRQ_STATUS2		0x2a4
-#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR		(1 << 0)
-#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR		(1 << 1)
-#define HOST_IRQ_STATUS2_CRC_ERR			(1 << 2)
-
-#define HOST_IRQ_MASK			0x2a8
-#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK			(1 << 0)
-#define HOST_IRQ_MASK_TX_PKT_DONE_MASK			(1 << 1)
-#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK		(1 << 2)
-#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK		(1 << 3)
-#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK		(1 << 4)
-#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK		(1 << 5)
-#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK		(1 << 6)
-#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK		(1 << 7)
-#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK	(1 << 8)
-#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK		(1 << 29)
-#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK		(1 << 30)
-#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK		(1 << 31)
-
-#define HOST_IRQ_MASK2			0x2ac
-#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK		(1 << 0)
-#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK		(1 << 1)
-#define HOST_IRQ_MASK2_CRC_ERR_MASK			(1 << 2)
-
-/* ------------------------------------- end -------------------------------- */
-
-#endif
diff --git a/drivers/video/starfive/sf_edp.c b/drivers/video/starfive/sf_edp.c
deleted file mode 100644
index bc6f6f9bc0..0000000000
--- a/drivers/video/starfive/sf_edp.c
+++ /dev/null
@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- */
-
-#include <common.h>
-#include <clk.h>
-#include <display.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <edid.h>
-#include <log.h>
-#include <malloc.h>
-#include <panel.h>
-#include <regmap.h>
-#include <reset.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-
-
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-#define DP_LINK_STATUS_SIZE 6
-
-#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
-#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
-
-#define RK3288_GRF_SOC_CON6	0x025c
-#define RK3288_GRF_SOC_CON12	0x0274
-#define RK3399_GRF_SOC_CON20	0x6250
-#define RK3399_GRF_SOC_CON25	0x6264
-
-enum rockchip_dp_types {
-	RK3288_DP = 0,
-	RK3399_EDP
-};
-
-struct rockchip_dp_data {
-	unsigned long reg_vop_big_little;
-	unsigned long reg_vop_big_little_sel;
-	unsigned long reg_ref_clk_sel;
-	unsigned long ref_clk_sel_bit;
-	enum rockchip_dp_types chip_type;
-};
-
-struct link_train {
-	unsigned char revision;
-	u8 link_rate;
-	u8 lane_count;
-};
-
-struct rk_edp_priv {
-	struct rk3288_edp *regs;
-	void *grf;
-	struct udevice *panel;
-	struct link_train link_train;
-	u8 train_set[4];
-};
-
-
-static int rk_edp_enable(struct udevice *dev, int panel_bpp,
-			 const struct display_timing *edid)
-{
-	return 0;
-}
-
-static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
-{
-	return 0;
-
-}
-
-static int rk_edp_of_to_plat(struct udevice *dev)
-{
-	return 0;
-}
-
-static int rk_edp_remove(struct udevice *dev)
-{
-	return 0;
-}
-
-static int rk_edp_probe(struct udevice *dev)
-{
-	return 0;
-}
-
-static const struct dm_display_ops dp_rockchip_ops = {
-	.read_edid = rk_edp_read_edid,
-	.enable = rk_edp_enable,
-};
-
-static const struct rockchip_dp_data rk3399_edp = {
-	.reg_vop_big_little = RK3399_GRF_SOC_CON20,
-	.reg_vop_big_little_sel = BIT(5),
-	.reg_ref_clk_sel = RK3399_GRF_SOC_CON25,
-	.ref_clk_sel_bit = BIT(11),
-	.chip_type = RK3399_EDP,
-};
-
-static const struct rockchip_dp_data rk3288_dp = {
-	.reg_vop_big_little = RK3288_GRF_SOC_CON6,
-	.reg_vop_big_little_sel = BIT(5),
-	.reg_ref_clk_sel = RK3288_GRF_SOC_CON12,
-	.ref_clk_sel_bit = BIT(4),
-	.chip_type = RK3288_DP,
-};
-
-static const struct udevice_id rockchip_dp_ids[] = {
-	{ .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp },
-	{ .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp },
-	{ }
-};
-
-U_BOOT_DRIVER(dp_rockchip) = {
-	.name	= "edp_rockchip",
-	.id	= UCLASS_DISPLAY,
-	.of_match = rockchip_dp_ids,
-	.ops	= &dp_rockchip_ops,
-	.of_to_plat	= rk_edp_of_to_plat,
-	.probe	= rk_edp_probe,
-	.remove	= rk_edp_remove,
-	.priv_auto	= sizeof(struct rk_edp_priv),
-};
diff --git a/drivers/video/starfive/sf_hdmi.c b/drivers/video/starfive/sf_hdmi.c
deleted file mode 100644
index 319080114f..0000000000
--- a/drivers/video/starfive/sf_hdmi.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <clk.h>
-#include <display.h>
-#include <dm.h>
-#include <dw_hdmi.h>
-#include <edid.h>
-#include <regmap.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <power/regulator.h>
-#include "sf_hdmi.h"
-
-static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp,
-			      const struct display_timing *edid)
-{
-	return 0;
-}
-
-int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
-{
- 	return 0;
-}
-
-static int rk3399_hdmi_of_to_plat(struct udevice *dev)
-{
-	return 0;
-}
-
-static int rk3399_hdmi_probe(struct udevice *dev)
-{
-	return 0;
-}
-
-static const struct dm_display_ops rk3399_hdmi_ops = {
-	.read_edid = rk_hdmi_read_edid,
-	.enable = rk3399_hdmi_enable,
-};
-
-static const struct udevice_id rk3399_hdmi_ids[] = {
-	{ .compatible = "rockchip,rk3288-dw-hdmi" },
-	{ }
-};
-
-U_BOOT_DRIVER(rk3399_hdmi_rockchip) = {
-	.name = "rk3399_hdmi_rockchip",
-	.id = UCLASS_DISPLAY,
-	.of_match = rk3399_hdmi_ids,
-	.ops = &rk3399_hdmi_ops,
-	.of_to_plat = rk3399_hdmi_of_to_plat,
-	.probe = rk3399_hdmi_probe,
-	.priv_auto	= sizeof(struct rk_hdmi_priv),
-};
diff --git a/drivers/video/starfive/sf_hdmi.h b/drivers/video/starfive/sf_hdmi.h
deleted file mode 100644
index 859a0b9ff3..0000000000
--- a/drivers/video/starfive/sf_hdmi.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#ifndef __RK_HDMI_H__
-#define __RK_HDMI_H__
-
-struct rkhdmi_driverdata {
-	/* configuration */
-	u8 i2c_clk_high;
-	u8 i2c_clk_low;
-	const char * const *regulator_names;
-	u32 regulator_names_cnt;
-	/* setters/getters */
-	int (*set_input_vop)(struct udevice *dev);
-	int (*clk_config)(struct udevice *dev);
-};
-
-struct rk_hdmi_priv {
-	struct dw_hdmi hdmi;
-	void *grf;
-};
-
-/**
- * rk_hdmi_read_edid() - read the attached HDMI/DVI monitor's EDID
- *
- * N.B.: The buffer should be large enough to hold 2 EDID blocks, as
- *       this function calls dw_hdmi_read_edid, which ignores buf_size
- *       argument and assumes that there's always enough space for 2
- *       EDID blocks.
- *
- * @dev:	device
- * @buf:	output buffer for the EDID
- * @buf_size:	number of bytes in the buffer
- * @return number of bytes read if OK, -ve if something went wrong
- */
-int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size);
-
-/**
- * rk_hdmi_probe_regulators() - probe (autoset + enable) regulators
- *
- * Probes a list of regulators by performing autoset and enable
- * operations on them.  The list of regulators is an array of string
- * pointers and any individual regulator-probe may fail without
- * counting as an error.
- *
- * @dev:	device
- * @names:	array of string-pointers to regulator names to probe
- * @cnt:	number of elements in the 'names' array
- */
-void rk_hdmi_probe_regulators(struct udevice *dev,
-			      const char * const *names, int cnt);
-/**
- * rk_hdmi_of_to_plat() - common of_to_plat implementation
- *
- * @dev:	device
- * @return 0 if OK, -ve if something went wrong
- */
-int rk_hdmi_of_to_plat(struct udevice *dev);
-
-/**
- * rk_hdmi_probe() - common probe implementation
- *
- * Performs the following, common initialisation steps:
- * 1. checks for HPD (i.e. a HDMI monitor being attached)
- * 2. initialises the Designware HDMI core
- * 3. initialises the Designware HDMI PHY
- *
- * @dev:	device
- * @return 0 if OK, -ve if something went wrong
- */
-int rk_hdmi_probe(struct udevice *dev);
-
-#endif
diff --git a/drivers/video/starfive/sf_lvds.c b/drivers/video/starfive/sf_lvds.c
deleted file mode 100644
index 54cabce628..0000000000
--- a/drivers/video/starfive/sf_lvds.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Rockchip Inc.
- */
-
-#include <common.h>
-#include <display.h>
-#include <dm.h>
-#include <edid.h>
-#include <log.h>
-#include <panel.h>
-#include <regmap.h>
-#include <syscon.h>
-#include <asm/global_data.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-
-#include <dt-bindings/clock/rk3288-cru.h>
-#include <dt-bindings/video/rk3288.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
- * struct rk_lvds_priv - private rockchip lvds display driver info
- *
- * @reg: LVDS register address
- * @grf: GRF register
- * @panel: Panel device that is used in driver
- *
- * @output: Output mode, decided single or double channel,
- *		LVDS or LVTLL
- * @format: Data format that RGB data will packing as
- */
-struct rk_lvds_priv {
-	void __iomem *regs;
-	struct udevice *panel;
-
-	int output;
-	int format;
-};
-
-int rk_lvds_enable(struct udevice *dev, int panel_bpp,
-		   const struct display_timing *edid)
-{
-	return 0;
-}
-
-int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
-{
-	return 0;
-}
-
-static int rk_lvds_of_to_plat(struct udevice *dev)
-{
-	return 0;
-}
-
-int rk_lvds_probe(struct udevice *dev)
-{
-
-	return 0;
-}
-
-static const struct dm_display_ops lvds_rockchip_ops = {
-	.read_timing = rk_lvds_read_timing,
-	.enable = rk_lvds_enable,
-};
-
-static const struct udevice_id rockchip_lvds_ids[] = {
-	{.compatible = "rockchip,rk3288-lvds"},
-	{}
-};
-
-U_BOOT_DRIVER(lvds_rockchip) = {
-	.name	= "lvds_rockchip",
-	.id	= UCLASS_DISPLAY,
-	.of_match = rockchip_lvds_ids,
-	.ops	= &lvds_rockchip_ops,
-	.of_to_plat	= rk_lvds_of_to_plat,
-	.probe	= rk_lvds_probe,
-	.priv_auto	= sizeof(struct rk_lvds_priv),
-};
diff --git a/drivers/video/starfive/sf_mipi.c b/drivers/video/starfive/sf_mipi.c
deleted file mode 100644
index 8c2bcea845..0000000000
--- a/drivers/video/starfive/sf_mipi.c
+++ /dev/null
@@ -1,566 +0,0 @@
-#include <common.h>
-#include <clk.h>
-#include <display.h>
-#include <dm.h>
-#include <log.h>
-#include <panel.h>
-#include <regmap.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <dm/uclass-internal.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <video_bridge.h>
-
-#include <dsi_host.h>
-#include <mipi_dsi.h>
-#include <reset.h>
-#include <video.h>
-
-#include <linux/iopoll.h>
-#include <linux/err.h>
-#include <power/regulator.h>
-#include <regmap.h>
-#include <syscon.h>
-#include "sf_mipi.h"
-
-static inline u32 sf_dphy_get_reg(void __iomem * io_addr, u32 shift, u32 mask)
-{
-	return (readl(io_addr) & mask) >> shift;
-}
-
-static inline void sf_dphy_set_reg(void __iomem * io_addr, u32 data, u32 shift, u32 mask)
-{
-    u32 tmp;
-    tmp = readl(io_addr);
-    tmp &= ~mask;
-    tmp |= (data << shift) & mask;
-    writel(tmp, io_addr);
-}
-
-static int dsi_phy_init(void *priv_data)
-{
-	struct mipi_dsi_device *device = priv_data;
-	struct udevice *dev = device->dev;
-	struct dsi_sf_priv *dsi = dev_get_priv(dev);
-
-	uint32_t temp;
-
-	temp = sf_dphy_get_reg(dsi->sys_reg, AON_GP_REG_SHIFT,AON_GP_REG_MASK);
-
-	if (!(temp & DPHY_TX_PSW_EN_MASK)) {
-		temp |= DPHY_TX_PSW_EN_MASK;
-		sf_dphy_set_reg(dsi->sys_reg, temp,AON_GP_REG_SHIFT,AON_GP_REG_MASK);
-	}
-
-	return 0;
-}
-
-static int is_pll_locked(void __iomem *phy_reg)
-{
-	return !sf_dphy_get_reg(phy_reg + 0x8,
-				RGS_CDTX_PLL_UNLOCK_SHIFT, RGS_CDTX_PLL_UNLOCK_MASK);
-}
-
-static void reset(int assert, void __iomem *phy_reg)
-{
-	sf_dphy_set_reg(phy_reg + 0x64, (!assert), RESETB_SHIFT, RESETB_MASK);
-
-	if (!assert) {
-		while(!is_pll_locked(phy_reg));
-	}
-}
-
-static inline void sys_delay(int cycles)
-{
-    while (cycles--);
-}
-
-int sys_mipi_dsi_set_ppi_txbyte_hs(int enable, void *priv_data)
-{
-	struct mipi_dsi_device *device = priv_data;
-	struct udevice *dev = device->dev;
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	static int status = 0;
-	int ret;
-	if (!enable && status) {
-		status = 0;
-		ret = reset_assert(&priv->txbytehs_rst);
-		if (ret < 0) {
-			return ret;
-		}
-	} else if (enable && !status) {
-		status = 1;
-		ret = reset_deassert(&priv->txbytehs_rst);
-		if (ret < 0) {
-			return ret;
-		}
-	}
-	sys_delay(100);
-	return 0;
-}
-
-static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
-{
-	struct mipi_dsi_device *device = priv_data;
-	struct udevice *dev = device->dev;
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	uint32_t bitrate;
-	unsigned long alignment;
-	int i;
-	int ret;
-	const struct m31_dphy_config *p;
-	const uint32_t AON_POWER_READY_N_active = 0;
-
-	debug("Set mode enable %ld\n",
-		mode_flags & MIPI_DSI_MODE_VIDEO);
-
-	if (!priv)
-		return;
-
-	bitrate = 750000000;//1188M 60fps
-
-	sf_dphy_set_reg(priv->phy_reg + 0x8, 0x10,
-					RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L2N_HSTX_RES_SHIFT, RG_CDTX_L2N_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L3N_HSTX_RES_SHIFT, RG_CDTX_L3N_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0x10, 0x10,
-					RG_CDTX_L4N_HSTX_RES_SHIFT, RG_CDTX_L4N_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0x8, 0x10,
-					RG_CDTX_L0P_HSTX_RES_SHIFT, RG_CDTX_L0P_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L1P_HSTX_RES_SHIFT, RG_CDTX_L1P_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L2P_HSTX_RES_SHIFT, RG_CDTX_L2P_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0xC, 0x10,
-					RG_CDTX_L3P_HSTX_RES_SHIFT, RG_CDTX_L3P_HSTX_RES_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0x10, 0x10,
-					RG_CDTX_L4P_HSTX_RES_SHIFT, RG_CDTX_L4P_HSTX_RES_MASK);
-
-	if (is_pll_locked(priv->phy_reg))
-		debug("Error: MIPI dphy-tx # PLL is not supposed to be LOCKED\n");
-	else
-		debug("MIPI dphy-tx # PLL is not LOCKED\n");
-
-	alignment = M31_DPHY_BITRATE_ALIGN;
-	if (bitrate % alignment) {
-		bitrate += alignment - (bitrate % alignment);
-	}
-
-	p = m31_dphy_configs;
-	for (i = 0; i < ARRAY_SIZE(m31_dphy_configs); i++, p++) {
-		if (p->bitrate == bitrate) {
-			sf_dphy_set_reg(priv->phy_reg + 0x64, M31_DPHY_REFCLK, REFCLK_IN_SEL_SHIFT, REFCLK_IN_SEL_MASK);
-
-			sf_dphy_set_reg(priv->phy_reg, AON_POWER_READY_N_active,
-							AON_POWER_READY_N_SHIFT, AON_POWER_READY_N_MASK);
-
-			sf_dphy_set_reg(priv->phy_reg, 0x0,
-							CFG_L0_SWAP_SEL_SHIFT, CFG_L0_SWAP_SEL_MASK);//Lane setting
-			sf_dphy_set_reg(priv->phy_reg, 0x1,
-							CFG_L1_SWAP_SEL_SHIFT, CFG_L1_SWAP_SEL_MASK);
-			sf_dphy_set_reg(priv->phy_reg, 0x4,
-							CFG_L2_SWAP_SEL_SHIFT, CFG_L2_SWAP_SEL_MASK);
-			sf_dphy_set_reg(priv->phy_reg, 0x2,
-							CFG_L3_SWAP_SEL_SHIFT, CFG_L3_SWAP_SEL_MASK);
-			sf_dphy_set_reg(priv->phy_reg, 0x3,
-							CFG_L4_SWAP_SEL_SHIFT, CFG_L4_SWAP_SEL_MASK);
-			//PLL setting
-			sf_dphy_set_reg(priv->phy_reg + 0x1c, 0x0,
-							RG_CDTX_PLL_SSC_EN_SHIFT, RG_CDTX_PLL_SSC_EN_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x18, 0x1,
-							RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT, RG_CDTX_PLL_LDO_STB_X2_EN_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x18, 0x1,
-							RG_CDTX_PLL_FM_EN_SHIFT, RG_CDTX_PLL_FM_EN_MASK);
-
-			sf_dphy_set_reg(priv->phy_reg + 0x18, p->pll_prev_div,
-							RG_CDTX_PLL_PRE_DIV_SHIFT, RG_CDTX_PLL_PRE_DIV_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x18, p->pll_fbk_int,
-							RG_CDTX_PLL_FBK_INT_SHIFT, RG_CDTX_PLL_FBK_INT_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x14, p->pll_fbk_fra,
-							RG_CDTX_PLL_FBK_FRA_SHIFT, RG_CDTX_PLL_FBK_FRA_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x28, p->extd_cycle_sel,
-							RG_EXTD_CYCLE_SEL_SHIFT, RG_EXTD_CYCLE_SEL_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x24, p->dlane_hs_pre_time,
-							RG_DLANE_HS_PRE_TIME_SHIFT, RG_DLANE_HS_PRE_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x24, p->dlane_hs_pre_time,
-							RG_DLANE_HS_PRE_TIME_SHIFT, RG_DLANE_HS_PRE_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x24, p->dlane_hs_zero_time,
-							RG_DLANE_HS_ZERO_TIME_SHIFT, RG_DLANE_HS_ZERO_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x24, p->dlane_hs_trail_time,
-							RG_DLANE_HS_TRAIL_TIME_SHIFT, RG_DLANE_HS_TRAIL_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x20, p->clane_hs_pre_time,
-							RG_CLANE_HS_PRE_TIME_SHIFT, RG_CLANE_HS_PRE_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x24, p->clane_hs_zero_time,
-							RG_CLANE_HS_ZERO_TIME_SHIFT, RG_CLANE_HS_ZERO_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x20, p->clane_hs_trail_time,
-							RG_CLANE_HS_TRAIL_TIME_SHIFT, RG_CLANE_HS_TRAIL_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x20, p->clane_hs_clk_pre_time,
-							RG_CLANE_HS_CLK_PRE_TIME_SHIFT, RG_CLANE_HS_CLK_PRE_TIME_MASK);
-			sf_dphy_set_reg(priv->phy_reg + 0x20, p->clane_hs_clk_post_time,
-							RG_CLANE_HS_CLK_POST_TIME_SHIFT, RG_CLANE_HS_CLK_POST_TIME_MASK);
-			break;
-		}
-	}
-	
-	reset(0, priv->phy_reg);
-	sf_dphy_set_reg(priv->phy_reg + 0x30, 0,
-					SCFG_PPI_C_READY_SEL_SHIFT, SCFG_PPI_C_READY_SEL_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0x30, 0,
-					SCFG_DSI_TXREADY_ESC_SEL_SHIFT, SCFG_DSI_TXREADY_ESC_SEL_MASK);
-	sf_dphy_set_reg(priv->phy_reg + 0x2c, 0x30,
-					SCFG_C_HS_PRE_ZERO_TIME_SHIFT, SCFG_C_HS_PRE_ZERO_TIME_MASK);
-	ret = clk_enable(&priv->dphy_txesc_clk);
-	if (ret) {
-		pr_err("failed to prepare/enable dphy_txesc_clk\n");
-		return;
-	}
-
-	ret = reset_deassert(&priv->dphy_sys);
-	if (ret < 0) {
-		pr_err("failed to deassert dphy_sys\n");
-		return;
-	}
-
-	ret = sys_mipi_dsi_set_ppi_txbyte_hs(1, priv_data);
-	return;
-}
-
-static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
-			     u32 lanes, u32 format, unsigned int *lane_mbps)
-{
-	return 0;
-}
-
-static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
-	.init = dsi_phy_init,
-	.get_lane_mbps = dsi_get_lane_mbps,
-	.post_set_mode = dsi_phy_post_set_mode,
-};
-
-static int dsi_sf_attach(struct udevice *dev)
-{
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	struct mipi_dsi_device *device = &priv->device;
-	struct mipi_dsi_panel_plat *mplat;
-	struct display_timing timings;
-	int ret;
-
-	ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
-	if (ret) {
-		printf("panel device error %d\n", ret);
-		return ret;
-	}
-	debug("%s,priv->panel->name = %s\n", __func__,priv->panel->name);
-
-	mplat = dev_get_plat(priv->panel);
-	mplat->device = &priv->device;
-	device->lanes = mplat->lanes;
-	device->format = mplat->format;
-	device->mode_flags = mplat->mode_flags;
-
-	ret = panel_get_display_timing(priv->panel, &timings);
-	if (ret) {
-		ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
-						   0, &timings);
-		if (ret) {
-			printf("decode display timing error %d\n", ret);
-			return ret;
-		}
-	}
-
-	ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
-	if (ret) {
-		printf("No video dsi host detected %d\n", ret);
-		return ret;
-	}
-
-	ret = dsi_host_init(priv->dsi_host, device, &timings,
-			mplat->lanes,
-			&dsi_stm_phy_ops);
-	if (ret) {
-		printf("failed to initialize mipi dsi host\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int dsi_sf_set_backlight(struct udevice *dev, int percent)
-{
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	int ret;
-
-	ret = dsi_host_enable(priv->dsi_host);
-	if (ret) {
-		printf("failed to enable mipi dsi host\n");
-		return ret;
-	}
-
-	ret = panel_enable_backlight(priv->panel);
-	if (ret) {
-		printf("panel %s enable backlight error %d\n",
-			priv->panel->name, ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int sf_mipi_of_to_plat(struct udevice *dev)
-{
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	int ret = 0;
-	priv->dsi_reg = dev_remap_addr_name(dev, "dsi");
-	if (!priv->dsi_reg)
-		return -EINVAL;
-
-	priv->phy_reg = dev_remap_addr_name(dev, "phy");
-	if (!priv->phy_reg)
-		return -EINVAL;
-
-	priv->sys_reg = dev_remap_addr_name(dev, "syscon");
-	if (!priv->phy_reg)
-		return -EINVAL;
-
-	ret = clk_get_by_name(dev, "sys", &priv->dsi_sys_clk);
-	if (ret) {
-		pr_err("clk_get_by_name(dsi_sys_clk) failed: %d", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "apb", &priv->apb_clk);
-	if (ret) {
-		pr_err("clk_get_by_name(apb_clk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "txesc", &priv->txesc_clk);
-	if (ret) {
-		pr_err("clk_get_by_name(txesc_clk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dpi", &priv->dpi_clk);
-	if (ret) {
-		pr_err("clk_get_by_name(dpi_clk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dphy_txesc", &priv->dphy_txesc_clk);
-	if (ret) {
-		pr_err("clk_get_by_name(dphy_txesc_clk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = reset_get_by_name(dev, "dsi_dpi", &priv->dpi_rst);
-	if (ret) {
-		pr_err("failed to get dpi_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-
-	ret = reset_get_by_name(dev, "dsi_apb", &priv->apb_rst);
-	if (ret) {
-		pr_err("failed to get apb_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "dsi_rxesc", &priv->rxesc_rst);
-	if (ret) {
-		pr_err("failed to get rxesc_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "dsi_sys", &priv->sys_rst);
-	if (ret) {
-		pr_err("failed to get sys_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "dsi_txbytehs", &priv->txbytehs_rst);
-	if (ret) {
-		pr_err("failed to get txbytehs_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-
-	ret = reset_get_by_name(dev, "dsi_txesc", &priv->txesc_rst);
-	if (ret) {
-		pr_err("failed to get txesc_rst reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "dphy_sys", &priv->dphy_sys);
-	if (ret) {
-		pr_err("failed to get dphy_sys reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "dphy_txbytehs", &priv->dphy_txbytehs);
-	if (ret) {
-		pr_err("failed to get dphy_txbytehs reset (ret=%d)\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int cdns_check_register_access(struct udevice *dev)
-{
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	const uint16_t ctrl_patterns[] = {0x0000, 0xffff, 0xa5a5, 0x5a5a};
-	int i;
-	uint32_t rd_val;
-
-	for (i = 0; i < ARRAY_SIZE_DSI(ctrl_patterns); i++) {
-		uint32_t temp = readl(priv->dsi_reg + TEST_GENERIC);
-		temp &= ~0xffff;
-		temp |= TEST_CTRL(ctrl_patterns[i]);
-		writel(temp, priv->dsi_reg + TEST_GENERIC);
-
-		rd_val = readl(priv->dsi_reg + TEST_GENERIC);
-		if (rd_val != temp) {
-			return 1;
-		}
-	}
-
-    return 0;
-}
-
-static int dsi_sf_probe(struct udevice *dev)
-{
-	struct dsi_sf_priv *priv = dev_get_priv(dev);
-	struct mipi_dsi_device *device = &priv->device;
-	int ret;
-	unsigned long rate;
-	uint32_t val;
-
-	device->dev = dev;
-
-	ret = dev_read_u32(dev, "data-lanes-num", &priv->data_lanes);
-	if (ret) {
-		printf("fail to get data lanes property %d\n", ret);
-		return 0;
-	}
-
-	ret = clk_enable(&priv->dsi_sys_clk);
-	if (ret < 0) {
-		pr_err("clk_enable(dsi_sys_clk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_enable(&priv->apb_clk);
-	if (ret < 0) {
-		pr_err("clk_enable(apb_clk) failed: %d\n", ret);
-		goto free_clock_apb_clk;
-	}
-
-	ret = clk_enable(&priv->txesc_clk);
-	if (ret < 0) {
-		pr_err("clk_enable(txesc_clk) failed: %d\n", ret);
-		goto free_clock_txesc_clk;
-	}
-
-	ret = clk_enable(&priv->dpi_clk);
-	if (ret < 0) {
-		pr_err("clk_enable(dpi_clk) failed: %d\n", ret);
-		goto free_clock_dpi_clk;
-	}
-
-	ret = reset_deassert(&priv->sys_rst);
-	if (ret < 0) {
-		pr_err("failed to deassert sys_rst\n");
-		goto free_reset;
-    }
-
-	ret = reset_deassert(&priv->apb_rst);
-	if (ret) {
-		pr_err("failed to deassert apb_rst reset (ret=%d)\n", ret);
-		goto free_reset;
-	}
-
-	ret = reset_deassert(&priv->txesc_rst);
-	if (ret) {
-		pr_err("failed to deassert txesc_rst reset (ret=%d)\n", ret);
-		goto free_reset;
-	}
-
-
-	ret = reset_deassert(&priv->rxesc_rst);
-	if (ret) {
-		pr_err("failed to deassert rxesc_rst reset (ret=%d)\n", ret);
-		goto free_reset;
-	}
-
-	ret = reset_deassert(&priv->dpi_rst);
-	if (ret) {
-		pr_err("failed to deassert dpi_rst reset (ret=%d)\n", ret);
-		goto free_reset;
-	}
-
-	rate = clk_get_rate(&priv->dsi_sys_clk);
-	debug("%s ok: dsi_sys_clk rate = %ld\n", __func__, rate);
-
-	val = readl(priv->dsi_reg + ID_REG);
-
-	debug("%s ok: ID_REG val = %08x\n", __func__, val);
-	if (REV_VENDOR_ID(val) != 0xcad) {
-		printf("invalid vendor id\n");
-		ret = -EINVAL;
-	}
-
-	ret = cdns_check_register_access(dev);
-    if (ret) {
-        printf("error: r/w test generic reg failed\n");
-    }
-
-	val = readl(priv->dsi_reg + IP_CONF);
-	priv->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
-	priv->rx_fifo_depth = RX_FIFO_DEPTH(val);
-
-	writel(0, priv->dsi_reg + MCTL_MAIN_DATA_CTL);
-	writel(0, priv->dsi_reg + MCTL_MAIN_EN);
-	writel(0, priv->dsi_reg + MCTL_MAIN_PHY_CTL);
-	/* Mask all interrupts before registering the IRQ handler. */
-	writel(0, priv->dsi_reg + MCTL_MAIN_STS_CTL);
-	writel(0, priv->dsi_reg + MCTL_DPHY_ERR_CTL1);
-	writel(0, priv->dsi_reg + CMD_MODE_STS_CTL);
-	writel(0, priv->dsi_reg + DIRECT_CMD_STS_CTL);
-	writel(0, priv->dsi_reg + DIRECT_CMD_RD_STS_CTL);
-	writel(0, priv->dsi_reg + VID_MODE_STS_CTL);
-	writel(0, priv->dsi_reg + TVG_STS_CTL);
-	writel(0, priv->dsi_reg + DPI_IRQ_EN);
-
-	return ret;
-
-free_reset:
-	clk_disable(&priv->dpi_clk);
-free_clock_dpi_clk:
-	clk_disable(&priv->txesc_clk);
-free_clock_txesc_clk:
-	clk_disable(&priv->apb_clk);
-free_clock_apb_clk:
-	clk_disable(&priv->dsi_sys_clk);
-
-	return ret;
-}
-
-struct video_bridge_ops sf_dsi_bridge_ops = {
-	.attach = dsi_sf_attach,
-	.set_backlight = dsi_sf_set_backlight,
-};
-
-static const struct udevice_id sf_mipi_dsi_ids[] = {
-	{ .compatible = "starfive,sf_mipi_dsi" },
-	{ }
-};
-
-U_BOOT_DRIVER(starfive_mipi_dsi) = {
-	.name	= "starfive_mipi_dsi",
-	.id	= UCLASS_VIDEO_BRIDGE,
-	.of_match = sf_mipi_dsi_ids,
-	.bind	= dm_scan_fdt_dev,
-	.of_to_plat = sf_mipi_of_to_plat,
-	.probe	= dsi_sf_probe,
-	.ops	= &sf_dsi_bridge_ops,
-	.priv_auto	  = sizeof(struct dsi_sf_priv),
-};
diff --git a/drivers/video/starfive/sf_mipi.h b/drivers/video/starfive/sf_mipi.h
deleted file mode 100644
index 21c82340ba..0000000000
--- a/drivers/video/starfive/sf_mipi.h
+++ /dev/null
@@ -1,820 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
- * Author: Eric Gao <eric.gao@rock-chips.com>
- */
-
-#ifndef __RK_MIPI_H
-#define __RK_MIPI_H
-
-#include <clk.h>
-#include <reset.h>
-#include <mipi_dsi.h>
-
-//sysrst registers
-#define SRST_ASSERT0		0x00
-#define SRST_STATUS0		0x04
-
-#define IP_CONF				0x0
-#define SP_HS_FIFO_DEPTH(x)		(((x) & GENMASK(30, 26)) >> 26)
-#define SP_LP_FIFO_DEPTH(x)		(((x) & GENMASK(25, 21)) >> 21)
-#define VRS_FIFO_DEPTH(x)		(((x) & GENMASK(20, 16)) >> 16)
-#define DIRCMD_FIFO_DEPTH(x)		(((x) & GENMASK(15, 13)) >> 13)
-#define SDI_IFACE_32			BIT(12)
-#define INTERNAL_DATAPATH_32		(0 << 10)
-#define INTERNAL_DATAPATH_16		(1 << 10)
-#define INTERNAL_DATAPATH_8		(3 << 10)
-#define INTERNAL_DATAPATH_SIZE		((x) & GENMASK(11, 10))
-#define NUM_IFACE(x)			((((x) & GENMASK(9, 8)) >> 8) + 1)
-#define MAX_LANE_NB(x)			(((x) & GENMASK(7, 6)) >> 6)
-#define RX_FIFO_DEPTH(x)		((x) & GENMASK(5, 0))
-
-#define MCTL_MAIN_DATA_CTL		0x4
-#define TE_MIPI_POLLING_EN		BIT(25)
-#define TE_HW_POLLING_EN		BIT(24)
-#define DISP_EOT_GEN			BIT(18)
-#define HOST_EOT_GEN			BIT(17)
-#define DISP_GEN_CHECKSUM		BIT(16)
-#define DISP_GEN_ECC			BIT(15)
-#define BTA_EN				BIT(14)
-#define READ_EN				BIT(13)
-#define REG_TE_EN			BIT(12)
-#define IF_TE_EN(x)			BIT(8 + (x))
-#define TVG_SEL				BIT(6)
-#define VID_EN				BIT(5)
-#define IF_VID_SELECT(x)		((x) << 2)
-#define IF_VID_SELECT_MASK		GENMASK(3, 2)
-#define IF_VID_MODE			BIT(1)
-#define LINK_EN				BIT(0)
-
-#define MCTL_MAIN_PHY_CTL		0x8
-#define HS_INVERT_DAT(x)		BIT(19 + ((x) * 2))
-#define SWAP_PINS_DAT(x)		BIT(18 + ((x) * 2))
-#define HS_INVERT_CLK			BIT(17)
-#define SWAP_PINS_CLK			BIT(16)
-#define HS_SKEWCAL_EN			BIT(15)
-#define WAIT_BURST_TIME(x)		((x) << 10)
-#define DATA_ULPM_EN(x)			BIT(6 + (x))
-#define CLK_ULPM_EN			BIT(5)
-#define CLK_CONTINUOUS			BIT(4)
-#define DATA_LANE_EN(x)			BIT((x) - 1)
-
-#define MCTL_MAIN_EN			0xc
-#define DATA_FORCE_STOP			BIT(17)
-#define CLK_FORCE_STOP			BIT(16)
-#define IF_EN(x)			BIT(13 + (x))
-#define DATA_LANE_ULPM_REQ(l)		BIT(9 + (l))
-#define CLK_LANE_ULPM_REQ		BIT(8)
-#define DATA_LANE_START(x)		BIT(4 + (x))
-#define CLK_LANE_EN			BIT(3)
-#define PLL_START			BIT(0)
-
-#define MCTL_DPHY_CFG0			0x10
-#define DPHY_C_RSTB			BIT(20)
-#define DPHY_D_RSTB(x)			GENMASK(15 + (x), 16)
-#define DPHY_PLL_PDN			BIT(10)
-#define DPHY_CMN_PDN			BIT(9)
-#define DPHY_C_PDN			BIT(8)
-#define DPHY_D_PDN(x)			GENMASK(3 + (x), 4)
-#define DPHY_ALL_D_PDN			GENMASK(7, 4)
-#define DPHY_PLL_PSO			BIT(1)
-#define DPHY_CMN_PSO			BIT(0)
-
-#define MCTL_DPHY_TIMEOUT1		0x14
-#define HSTX_TIMEOUT(x)			((x) << 4)
-#define HSTX_TIMEOUT_MAX		GENMASK(17, 0)
-#define CLK_DIV(x)			(x)
-#define CLK_DIV_MAX			GENMASK(3, 0)
-
-#define MCTL_DPHY_TIMEOUT2		0x18
-#define LPRX_TIMEOUT(x)			(x)
-
-#define MCTL_ULPOUT_TIME		0x1c
-#define DATA_LANE_ULPOUT_TIME(x)	((x) << 9)
-#define CLK_LANE_ULPOUT_TIME(x)		(x)
-
-#define MCTL_3DVIDEO_CTL		0x20
-#define VID_VSYNC_3D_EN			BIT(7)
-#define VID_VSYNC_3D_LR			BIT(5)
-#define VID_VSYNC_3D_SECOND_EN		BIT(4)
-#define VID_VSYNC_3DFORMAT_LINE		(0 << 2)
-#define VID_VSYNC_3DFORMAT_FRAME	(1 << 2)
-#define VID_VSYNC_3DFORMAT_PIXEL	(2 << 2)
-#define VID_VSYNC_3DMODE_OFF		0
-#define VID_VSYNC_3DMODE_PORTRAIT	1
-#define VID_VSYNC_3DMODE_LANDSCAPE	2
-
-#define MCTL_MAIN_STS			0x24
-#define MCTL_MAIN_STS_CTL		0x130
-#define MCTL_MAIN_STS_CLR		0x150
-#define MCTL_MAIN_STS_FLAG		0x170
-#define HS_SKEWCAL_DONE			BIT(11)
-#define IF_UNTERM_PKT_ERR(x)		BIT(8 + (x))
-#define LPRX_TIMEOUT_ERR		BIT(7)
-#define HSTX_TIMEOUT_ERR		BIT(6)
-#define DATA_LANE_RDY(l)		BIT(2 + (l))
-#define CLK_LANE_RDY			BIT(1)
-#define PLL_LOCKED			BIT(0)
-
-#define MCTL_DPHY_ERR			0x28
-#define MCTL_DPHY_ERR_CTL1		0x148
-#define MCTL_DPHY_ERR_CLR		0x168
-#define MCTL_DPHY_ERR_FLAG		0x188
-#define ERR_CONT_LP(x, l)		BIT(18 + ((x) * 4) + (l))
-#define ERR_CONTROL(l)			BIT(14 + (l))
-#define ERR_SYNESC(l)			BIT(10 + (l))
-#define ERR_ESC(l)			BIT(6 + (l))
-
-#define MCTL_DPHY_ERR_CTL2		0x14c
-#define ERR_CONT_LP_EDGE(x, l)		BIT(12 + ((x) * 4) + (l))
-#define ERR_CONTROL_EDGE(l)		BIT(8 + (l))
-#define ERR_SYN_ESC_EDGE(l)		BIT(4 + (l))
-#define ERR_ESC_EDGE(l)			BIT(0 + (l))
-
-#define MCTL_LANE_STS			0x2c
-#define PPI_C_TX_READY_HS		BIT(18)
-#define DPHY_PLL_LOCK			BIT(17)
-#define PPI_D_RX_ULPS_ESC(x)		(((x) & GENMASK(15, 12)) >> 12)
-#define LANE_STATE_START		0
-#define LANE_STATE_IDLE			1
-#define LANE_STATE_WRITE		2
-#define LANE_STATE_ULPM			3
-#define LANE_STATE_READ			4
-#define DATA_LANE_STATE(l, val)		\
-	(((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
-#define CLK_LANE_STATE_HS		2
-#define CLK_LANE_STATE(val)		((val) & GENMASK(1, 0))
-
-#define DSC_MODE_CTL			0x30
-#define DSC_MODE_EN			BIT(0)
-
-#define DSC_CMD_SEND			0x34
-#define DSC_SEND_PPS			BIT(0)
-#define DSC_EXECUTE_QUEUE		BIT(1)
-
-#define DSC_PPS_WRDAT			0x38
-
-#define DSC_MODE_STS			0x3c
-#define DSC_PPS_DONE			BIT(1)
-#define DSC_EXEC_DONE			BIT(2)
-
-#define CMD_MODE_CTL			0x70
-#define IF_LP_EN(x)			BIT(9 + (x))
-#define IF_VCHAN_ID(x, c)		((c) << ((x) * 2))
-
-#define CMD_MODE_CTL2			0x74
-#define TE_TIMEOUT(x)			((x) << 11)
-#define FILL_VALUE(x)			((x) << 3)
-#define ARB_IF_WITH_HIGHEST_PRIORITY(x)	((x) << 1)
-#define ARB_ROUND_ROBIN_MODE		BIT(0)
-
-#define CMD_MODE_STS			0x78
-#define CMD_MODE_STS_CTL		0x134
-#define CMD_MODE_STS_CLR		0x154
-#define CMD_MODE_STS_FLAG		0x174
-#define ERR_IF_UNDERRUN(x)		BIT(4 + (x))
-#define ERR_UNWANTED_READ		BIT(3)
-#define ERR_TE_MISS			BIT(2)
-#define ERR_NO_TE			BIT(1)
-#define CSM_RUNNING			BIT(0)
-
-#define DIRECT_CMD_SEND			0x80
-
-#define DIRECT_CMD_MAIN_SETTINGS	0x84
-#define TRIGGER_VAL(x)			((x) << 25)
-#define CMD_LP_EN			BIT(24)
-#define CMD_SIZE(x)			((x) << 16)
-#define CMD_VCHAN_ID(x)			((x) << 14)
-#define CMD_DATATYPE(x)			((x) << 8)
-#define CMD_LONG			BIT(3)
-#define WRITE_CMD			0
-#define READ_CMD			1
-#define TE_REQ				4
-#define TRIGGER_REQ			5
-#define BTA_REQ				6
-
-#define DIRECT_CMD_STS			0x88
-#define DIRECT_CMD_STS_CTL		0x138
-#define DIRECT_CMD_STS_CLR		0x158
-#define DIRECT_CMD_STS_FLAG		0x178
-#define RCVD_ACK_VAL(val)		((val) >> 16)
-#define RCVD_TRIGGER_VAL(val)		(((val) & GENMASK(14, 11)) >> 11)
-#define READ_COMPLETED_WITH_ERR		BIT(10)
-#define BTA_FINISHED			BIT(9)
-#define BTA_COMPLETED			BIT(8)
-#define TE_RCVD				BIT(7)
-#define TRIGGER_RCVD			BIT(6)
-#define ACK_WITH_ERR_RCVD		BIT(5)
-#define ACK_RCVD			BIT(4)
-#define READ_COMPLETED			BIT(3)
-#define TRIGGER_COMPLETED		BIT(2)
-#define WRITE_COMPLETED			BIT(1)
-
-#define SENDING_CMD			BIT(0)
-
-#define DIRECT_CMD_STOP_READ		0x8c
-
-#define DIRECT_CMD_WRDATA		0x90
-
-#define DIRECT_CMD_FIFO_RST		0x94
-
-#define DIRECT_CMD_RDDATA		0xa0
-
-#define DIRECT_CMD_RD_PROPS		0xa4
-#define RD_DCS				BIT(18)
-#define RD_VCHAN_ID(val)		(((val) >> 16) & GENMASK(1, 0))
-#define RD_SIZE(val)			((val) & GENMASK(15, 0))
-
-#define DIRECT_CMD_RD_STS		0xa8
-#define DIRECT_CMD_RD_STS_CTL		0x13c
-#define DIRECT_CMD_RD_STS_CLR		0x15c
-#define DIRECT_CMD_RD_STS_FLAG		0x17c
-#define ERR_EOT_WITH_ERR		BIT(8)
-#define ERR_MISSING_EOT			BIT(7)
-#define ERR_WRONG_LENGTH		BIT(6)
-#define ERR_OVERSIZE			BIT(5)
-#define ERR_RECEIVE			BIT(4)
-#define ERR_UNDECODABLE			BIT(3)
-#define ERR_CHECKSUM			BIT(2)
-#define ERR_UNCORRECTABLE		BIT(1)
-#define ERR_FIXED			BIT(0)
-
-#define VID_MAIN_CTL			0xb0
-#define VID_IGNORE_MISS_VSYNC		BIT(31)
-#define VID_FIELD_SW			BIT(28)
-#define VID_INTERLACED_EN		BIT(27)
-#define RECOVERY_MODE(x)		((x) << 25)
-#define RECOVERY_MODE_NEXT_HSYNC	0
-#define RECOVERY_MODE_NEXT_STOP_POINT	2
-#define RECOVERY_MODE_NEXT_VSYNC	3
-#define REG_BLKEOL_MODE(x)		((x) << 23)
-#define REG_BLKLINE_MODE(x)		((x) << 21)
-#define REG_BLK_MODE_NULL_PKT		0
-#define REG_BLK_MODE_BLANKING_PKT	1
-#define REG_BLK_MODE_LP			2
-#define SYNC_PULSE_HORIZONTAL		BIT(20)
-#define SYNC_PULSE_ACTIVE		BIT(19)
-#define BURST_MODE			BIT(18)
-#define VID_PIXEL_MODE_MASK		GENMASK(17, 14)
-#define VID_PIXEL_MODE_RGB565		(0 << 14)
-#define VID_PIXEL_MODE_RGB666_PACKED	(1 << 14)
-#define VID_PIXEL_MODE_RGB666		(2 << 14)
-#define VID_PIXEL_MODE_RGB888		(3 << 14)
-#define VID_PIXEL_MODE_RGB101010	(4 << 14)
-#define VID_PIXEL_MODE_RGB121212	(5 << 14)
-#define VID_PIXEL_MODE_YUV420		(8 << 14)
-#define VID_PIXEL_MODE_YUV422_PACKED	(9 << 14)
-#define VID_PIXEL_MODE_YUV422		(10 << 14)
-#define VID_PIXEL_MODE_YUV422_24B	(11 << 14)
-#define VID_PIXEL_MODE_DSC_COMP		(12 << 14)
-#define VID_DATATYPE(x)			((x) << 8)
-#define VID_VIRTCHAN_ID(iface, x)	((x) << (4 + (iface) * 2))
-#define STOP_MODE(x)			((x) << 2)
-#define START_MODE(x)			(x)
-
-#define VID_VSIZE1			0xb4
-#define VFP_LEN(x)			((x) << 12)
-#define VBP_LEN(x)			((x) << 6)
-#define VSA_LEN(x)			(x)
-
-#define VID_VSIZE2			0xb8
-#define VACT_LEN(x)			(x)
-
-#define VID_HSIZE1			0xc0
-#define HBP_LEN(x)			((x) << 16)
-#define HSA_LEN(x)			(x)
-
-#define VID_HSIZE2			0xc4
-#define HFP_LEN(x)			((x) << 16)
-#define HACT_LEN(x)			(x)
-
-#define VID_BLKSIZE1			0xcc
-#define BLK_EOL_PKT_LEN(x)		((x) << 15)
-#define BLK_LINE_EVENT_PKT_LEN(x)	(x)
-
-#define VID_BLKSIZE2			0xd0
-#define BLK_LINE_PULSE_PKT_LEN(x)	(x)
-
-#define VID_PKT_TIME			0xd8
-#define BLK_EOL_DURATION(x)		(x)
-
-#define VID_DPHY_TIME			0xdc
-#define REG_WAKEUP_TIME(x)		((x) << 17)
-#define REG_LINE_DURATION(x)		(x)
-
-#define VID_ERR_COLOR1			0xe0
-#define COL_GREEN(x)			((x) << 12)
-#define COL_RED(x)			(x)
-
-#define VID_ERR_COLOR2			0xe4
-#define PAD_VAL(x)			((x) << 12)
-#define COL_BLUE(x)			(x)
-
-#define VID_VPOS			0xe8
-#define LINE_VAL(val)			(((val) & GENMASK(14, 2)) >> 2)
-#define LINE_POS(val)			((val) & GENMASK(1, 0))
-
-#define VID_HPOS			0xec
-#define HORIZ_VAL(val)			(((val) & GENMASK(17, 3)) >> 3)
-#define HORIZ_POS(val)			((val) & GENMASK(2, 0))
-
-#define VID_MODE_STS			0xf0
-#define VID_MODE_STS_CTL		0x140
-#define VID_MODE_STS_CLR		0x160
-#define VID_MODE_STS_FLAG		0x180
-#define VSG_RECOVERY			BIT(10)
-#define ERR_VRS_WRONG_LEN		BIT(9)
-#define ERR_LONG_READ			BIT(8)
-#define ERR_LINE_WRITE			BIT(7)
-#define ERR_BURST_WRITE			BIT(6)
-#define ERR_SMALL_HEIGHT		BIT(5)
-#define ERR_SMALL_LEN			BIT(4)
-#define ERR_MISSING_VSYNC		BIT(3)
-#define ERR_MISSING_HSYNC		BIT(2)
-#define ERR_MISSING_DATA		BIT(1)
-#define VSG_RUNNING			BIT(0)
-
-#define VID_VCA_SETTING1		0xf4
-#define BURST_LP			BIT(16)
-#define MAX_BURST_LIMIT(x)		(x)
-
-#define VID_VCA_SETTING2		0xf8
-#define MAX_LINE_LIMIT(x)		((x) << 16)
-#define EXACT_BURST_LIMIT(x)		(x)
-
-#define TVG_CTL				0xfc
-#define TVG_STRIPE_SIZE(x)		((x) << 5)
-#define TVG_MODE_MASK			GENMASK(4, 3)
-#define TVG_MODE_SINGLE_COLOR		(0 << 3)
-#define TVG_MODE_VSTRIPES		(2 << 3)
-#define TVG_MODE_HSTRIPES		(3 << 3)
-#define TVG_STOPMODE_MASK		GENMASK(2, 1)
-#define TVG_STOPMODE_EOF		(0 << 1)
-#define TVG_STOPMODE_EOL		(1 << 1)
-#define TVG_STOPMODE_NOW		(2 << 1)
-#define TVG_RUN				BIT(0)
-
-#define TVG_IMG_SIZE			0x100
-#define TVG_NBLINES(x)			((x) << 16)
-#define TVG_LINE_SIZE(x)		(x)
-
-#define TVG_COLOR1			0x104
-#define TVG_COL1_GREEN(x)		((x) << 12)
-#define TVG_COL1_RED(x)			(x)
-
-#define TVG_COLOR1_BIS			0x108
-#define TVG_COL1_BLUE(x)		(x)
-
-#define TVG_COLOR2			0x10c
-#define TVG_COL2_GREEN(x)		((x) << 12)
-#define TVG_COL2_RED(x)			(x)
-
-#define TVG_COLOR2_BIS			0x110
-#define TVG_COL2_BLUE(x)		(x)
-
-#define TVG_STS				0x114
-#define TVG_STS_CTL			0x144
-#define TVG_STS_CLR			0x164
-#define TVG_STS_FLAG			0x184
-#define TVG_STS_RUNNING			BIT(0)
-
-#define STS_CTL_EDGE(e)			((e) << 16)
-
-#define DPHY_LANES_MAP			0x198
-#define DAT_REMAP_CFG(b, l)		((l) << ((b) * 8))
-
-#define DPI_IRQ_EN			0x1a0
-#define DPI_IRQ_CLR			0x1a4
-#define DPI_IRQ_STS			0x1a8
-#define PIXEL_BUF_OVERFLOW		BIT(0)
-
-#define DPI_CFG				0x1ac
-#define DPI_CFG_FIFO_DEPTH(x)		((x) >> 16)
-#define DPI_CFG_FIFO_LEVEL(x)		((x) & GENMASK(15, 0))
-
-#define TEST_GENERIC			0x1f0
-#define TEST_STATUS(x)			((x) >> 16)
-#define TEST_CTRL(x)			(x)
-
-#define ID_REG				0x1fc
-#define REV_VENDOR_ID(x)		(((x) & GENMASK(31, 20)) >> 20)
-#define REV_PRODUCT_ID(x)		(((x) & GENMASK(19, 12)) >> 12)
-#define REV_HW(x)			(((x) & GENMASK(11, 8)) >> 8)
-#define REV_MAJOR(x)			(((x) & GENMASK(7, 4)) >> 4)
-#define REV_MINOR(x)			((x) & GENMASK(3, 0))
-
-#define DSI_OUTPUT_PORT			0
-#define DSI_INPUT_PORT(inputid)		(1 + (inputid))
-
-#define DSI_HBP_FRAME_OVERHEAD		12
-#define DSI_HSA_FRAME_OVERHEAD		14
-#define DSI_HFP_FRAME_OVERHEAD		6
-#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD	4
-#define DSI_BLANKING_FRAME_OVERHEAD	6
-#define DSI_NULL_FRAME_OVERHEAD		6
-#define DSI_EOT_PKT_SIZE		4
-
-#define ARRAY_SIZE_DSI(x) (sizeof(x) / sizeof((x)[0]))
-#define TEST_CTRL(x)                    (x)
-
-#define  AON_POWER_READY_N_WIDTH             0x1U
-#define  AON_POWER_READY_N_SHIFT             0x0U
-#define  AON_POWER_READY_N_MASK              0x1U
-#define  CFG_CKLANE_SET_WIDTH                0x5U
-#define  CFG_CKLANE_SET_SHIFT                0x1U
-#define  CFG_CKLANE_SET_MASK                 0x3EU
-#define  CFG_DATABUS16_SEL_WIDTH             0x1U
-#define  CFG_DATABUS16_SEL_SHIFT             0x6U
-#define  CFG_DATABUS16_SEL_MASK              0x40U
-#define  CFG_DPDN_SWAP_WIDTH                 0x5U
-#define  CFG_DPDN_SWAP_SHIFT                 0x7U
-#define  CFG_DPDN_SWAP_MASK                  0xF80U
-#define  CFG_L0_SWAP_SEL_WIDTH               0x3U
-#define  CFG_L0_SWAP_SEL_SHIFT               0xCU
-#define  CFG_L0_SWAP_SEL_MASK                0x7000U
-#define  CFG_L1_SWAP_SEL_WIDTH               0x3U
-#define  CFG_L1_SWAP_SEL_SHIFT               0xFU
-#define  CFG_L1_SWAP_SEL_MASK                0x38000U
-#define  CFG_L2_SWAP_SEL_WIDTH               0x3U
-#define  CFG_L2_SWAP_SEL_SHIFT               0x12U
-#define  CFG_L2_SWAP_SEL_MASK                0x1C0000U
-#define  CFG_L3_SWAP_SEL_WIDTH               0x3U
-#define  CFG_L3_SWAP_SEL_SHIFT               0x15U
-#define  CFG_L3_SWAP_SEL_MASK                0xE00000U
-#define  CFG_L4_SWAP_SEL_WIDTH               0x3U
-#define  CFG_L4_SWAP_SEL_SHIFT               0x18U
-#define  CFG_L4_SWAP_SEL_MASK                0x7000000U
-#define  MPOSV_31_0__WIDTH                   0x20U
-#define  MPOSV_31_0__SHIFT                   0x0U
-#define  MPOSV_31_0__MASK                    0xFFFFFFFFU
-#define  MPOSV_46_32__WIDTH                  0xFU
-#define  MPOSV_46_32__SHIFT                  0x0U
-#define  MPOSV_46_32__MASK                   0x7FFFU
-#define  RGS_CDTX_PLL_FM_CPLT_WIDTH          0x1U
-#define  RGS_CDTX_PLL_FM_CPLT_SHIFT          0xFU
-#define  RGS_CDTX_PLL_FM_CPLT_MASK           0x8000U
-#define  RGS_CDTX_PLL_FM_OVER_WIDTH          0x1U
-#define  RGS_CDTX_PLL_FM_OVER_SHIFT          0x10U
-#define  RGS_CDTX_PLL_FM_OVER_MASK           0x10000U
-#define  RGS_CDTX_PLL_FM_UNDER_WIDTH         0x1U
-#define  RGS_CDTX_PLL_FM_UNDER_SHIFT         0x11U
-#define  RGS_CDTX_PLL_FM_UNDER_MASK          0x20000U
-#define  RGS_CDTX_PLL_UNLOCK_WIDTH           0x1U
-#define  RGS_CDTX_PLL_UNLOCK_SHIFT           0x12U
-#define  RGS_CDTX_PLL_UNLOCK_MASK            0x40000U
-#define  RG_CDTX_L0N_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L0N_HSTX_RES_SHIFT          0x13U
-#define  RG_CDTX_L0N_HSTX_RES_MASK           0xF80000U
-#define  RG_CDTX_L0P_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L0P_HSTX_RES_SHIFT          0x18U
-#define  RG_CDTX_L0P_HSTX_RES_MASK           0x1F000000U
-
-#define  RG_CDTX_L1N_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L1N_HSTX_RES_SHIFT          0x0U
-#define  RG_CDTX_L1N_HSTX_RES_MASK           0x1FU
-#define  RG_CDTX_L1P_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L1P_HSTX_RES_SHIFT          0x5U
-#define  RG_CDTX_L1P_HSTX_RES_MASK           0x3E0U
-#define  RG_CDTX_L2N_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L2N_HSTX_RES_SHIFT          0xAU
-#define  RG_CDTX_L2N_HSTX_RES_MASK           0x7C00U
-#define  RG_CDTX_L2P_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L2P_HSTX_RES_SHIFT          0xFU
-#define  RG_CDTX_L2P_HSTX_RES_MASK           0xF8000U
-#define  RG_CDTX_L3N_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L3N_HSTX_RES_SHIFT          0x14U
-#define  RG_CDTX_L3N_HSTX_RES_MASK           0x1F00000U
-#define  RG_CDTX_L3P_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L3P_HSTX_RES_SHIFT          0x19U
-#define  RG_CDTX_L3P_HSTX_RES_MASK           0x3E000000U
-
-#define  RG_CDTX_L4N_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L4N_HSTX_RES_SHIFT          0x0U
-#define  RG_CDTX_L4N_HSTX_RES_MASK           0x1FU
-#define  RG_CDTX_L4P_HSTX_RES_WIDTH          0x5U
-#define  RG_CDTX_L4P_HSTX_RES_SHIFT          0x5U
-#define  RG_CDTX_L4P_HSTX_RES_MASK           0x3E0U
-
-#define  RG_CDTX_PLL_FBK_FRA_WIDTH           0x18U
-#define  RG_CDTX_PLL_FBK_FRA_SHIFT           0x0U
-#define  RG_CDTX_PLL_FBK_FRA_MASK            0xFFFFFFU
-
-#define  RG_CDTX_PLL_FBK_INT_WIDTH           0x9U
-#define  RG_CDTX_PLL_FBK_INT_SHIFT           0x0U
-#define  RG_CDTX_PLL_FBK_INT_MASK            0x1FFU
-#define  RG_CDTX_PLL_FM_EN_WIDTH             0x1U
-#define  RG_CDTX_PLL_FM_EN_SHIFT             0x9U
-#define  RG_CDTX_PLL_FM_EN_MASK              0x200U
-#define  RG_CDTX_PLL_LDO_STB_X2_EN_WIDTH     0x1U
-#define  RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT     0xAU
-#define  RG_CDTX_PLL_LDO_STB_X2_EN_MASK      0x400U
-#define  RG_CDTX_PLL_PRE_DIV_WIDTH           0x2U
-#define  RG_CDTX_PLL_PRE_DIV_SHIFT           0xBU
-#define  RG_CDTX_PLL_PRE_DIV_MASK            0x1800U
-#define  RG_CDTX_PLL_SSC_DELTA_WIDTH         0x12U
-#define  RG_CDTX_PLL_SSC_DELTA_SHIFT         0xDU
-#define  RG_CDTX_PLL_SSC_DELTA_MASK          0x7FFFE000U
-
-#define  RG_CDTX_PLL_SSC_DELTA_INIT_WIDTH    0x12U
-#define  RG_CDTX_PLL_SSC_DELTA_INIT_SHIFT    0x0U
-#define  RG_CDTX_PLL_SSC_DELTA_INIT_MASK     0x3FFFFU
-#define  RG_CDTX_PLL_SSC_EN_WIDTH            0x1U
-#define  RG_CDTX_PLL_SSC_EN_SHIFT            0x12U
-#define  RG_CDTX_PLL_SSC_EN_MASK             0x40000U
-#define  RG_CDTX_PLL_SSC_PRD_WIDTH           0xAU
-#define  RG_CDTX_PLL_SSC_PRD_SHIFT           0x13U
-#define  RG_CDTX_PLL_SSC_PRD_MASK            0x1FF80000U
-
-#define  RG_CLANE_HS_CLK_POST_TIME_WIDTH     0x8U
-#define  RG_CLANE_HS_CLK_POST_TIME_SHIFT     0x0U
-#define  RG_CLANE_HS_CLK_POST_TIME_MASK      0xFFU
-#define  RG_CLANE_HS_CLK_PRE_TIME_WIDTH      0x8U
-#define  RG_CLANE_HS_CLK_PRE_TIME_SHIFT      0x8U
-#define  RG_CLANE_HS_CLK_PRE_TIME_MASK       0xFF00U
-#define  RG_CLANE_HS_PRE_TIME_WIDTH          0x8U
-#define  RG_CLANE_HS_PRE_TIME_SHIFT          0x10U
-#define  RG_CLANE_HS_PRE_TIME_MASK           0xFF0000U
-#define  RG_CLANE_HS_TRAIL_TIME_WIDTH        0x8U
-#define  RG_CLANE_HS_TRAIL_TIME_SHIFT        0x18U
-#define  RG_CLANE_HS_TRAIL_TIME_MASK         0xFF000000U
-
-#define  RG_CLANE_HS_ZERO_TIME_WIDTH         0x8U
-#define  RG_CLANE_HS_ZERO_TIME_SHIFT         0x0U
-#define  RG_CLANE_HS_ZERO_TIME_MASK          0xFFU
-#define  RG_DLANE_HS_PRE_TIME_WIDTH          0x8U
-#define  RG_DLANE_HS_PRE_TIME_SHIFT          0x8U
-#define  RG_DLANE_HS_PRE_TIME_MASK           0xFF00U
-#define  RG_DLANE_HS_TRAIL_TIME_WIDTH        0x8U
-#define  RG_DLANE_HS_TRAIL_TIME_SHIFT        0x10U
-#define  RG_DLANE_HS_TRAIL_TIME_MASK         0xFF0000U
-#define  RG_DLANE_HS_ZERO_TIME_WIDTH         0x8U
-#define  RG_DLANE_HS_ZERO_TIME_SHIFT         0x18U
-#define  RG_DLANE_HS_ZERO_TIME_MASK          0xFF000000U
-
-#define  RG_EXTD_CYCLE_SEL_WIDTH             0x3U
-#define  RG_EXTD_CYCLE_SEL_SHIFT             0x0U
-#define  RG_EXTD_CYCLE_SEL_MASK              0x7U
-
-#define  SCFG_C_HS_PRE_ZERO_TIME_WIDTH       0x20U
-#define  SCFG_C_HS_PRE_ZERO_TIME_SHIFT       0x0U
-#define  SCFG_C_HS_PRE_ZERO_TIME_MASK        0xFFFFFFFFU
-
-#define  SCFG_DPHY_SRC_SEL_WIDTH             0x1U
-#define  SCFG_DPHY_SRC_SEL_SHIFT             0x0U
-#define  SCFG_DPHY_SRC_SEL_MASK              0x1U
-#define  SCFG_DSI_TXREADY_ESC_SEL_WIDTH      0x2U
-#define  SCFG_DSI_TXREADY_ESC_SEL_SHIFT      0x1U
-#define  SCFG_DSI_TXREADY_ESC_SEL_MASK       0x6U
-#define  SCFG_PPI_C_READY_SEL_WIDTH          0x2U
-#define  SCFG_PPI_C_READY_SEL_SHIFT          0x3U
-#define  SCFG_PPI_C_READY_SEL_MASK           0x18U
-#define  VCONTROL_WIDTH                      0x5U
-#define  VCONTROL_SHIFT                      0x5U
-#define  VCONTROL_MASK                       0x3E0U
-
-#define  XCFGI_DW00_WIDTH                    0x20U
-#define  XCFGI_DW00_SHIFT                    0x0U
-#define  XCFGI_DW00_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW01_WIDTH                    0x20U
-#define  XCFGI_DW01_SHIFT                    0x0U
-#define  XCFGI_DW01_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW02_WIDTH                    0x20U
-#define  XCFGI_DW02_SHIFT                    0x0U
-#define  XCFGI_DW02_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW03_WIDTH                    0x20U
-#define  XCFGI_DW03_SHIFT                    0x0U
-#define  XCFGI_DW03_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW04_WIDTH                    0x20U
-#define  XCFGI_DW04_SHIFT                    0x0U
-#define  XCFGI_DW04_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW05_WIDTH                    0x20U
-#define  XCFGI_DW05_SHIFT                    0x0U
-#define  XCFGI_DW05_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW06_WIDTH                    0x20U
-#define  XCFGI_DW06_SHIFT                    0x0U
-#define  XCFGI_DW06_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW07_WIDTH                    0x20U
-#define  XCFGI_DW07_SHIFT                    0x0U
-#define  XCFGI_DW07_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW08_WIDTH                    0x20U
-#define  XCFGI_DW08_SHIFT                    0x0U
-#define  XCFGI_DW08_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW09_WIDTH                    0x20U
-#define  XCFGI_DW09_SHIFT                    0x0U
-#define  XCFGI_DW09_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW0A_WIDTH                    0x20U
-#define  XCFGI_DW0A_SHIFT                    0x0U
-#define  XCFGI_DW0A_MASK                     0xFFFFFFFFU
-
-#define  XCFGI_DW0B_WIDTH                    0x20U
-#define  XCFGI_DW0B_SHIFT                    0x0U
-#define  XCFGI_DW0B_MASK                     0xFFFFFFFFU
-
-#define  DBG1_MUX_DOUT_WIDTH                 0x8U
-#define  DBG1_MUX_DOUT_SHIFT                 0x0U
-#define  DBG1_MUX_DOUT_MASK                  0xFFU
-#define  DBG1_MUX_SEL_WIDTH                  0x5U
-#define  DBG1_MUX_SEL_SHIFT                  0x8U
-#define  DBG1_MUX_SEL_MASK                   0x1F00U
-#define  DBG2_MUX_DOUT_WIDTH                 0x8U
-#define  DBG2_MUX_DOUT_SHIFT                 0xDU
-#define  DBG2_MUX_DOUT_MASK                  0x1FE000U
-#define  DBG2_MUX_SEL_WIDTH                  0x5U
-#define  DBG2_MUX_SEL_SHIFT                  0x15U
-#define  DBG2_MUX_SEL_MASK                   0x3E00000U
-#define  REFCLK_IN_SEL_WIDTH                 0x3U
-#define  REFCLK_IN_SEL_SHIFT                 0x1AU
-#define  REFCLK_IN_SEL_MASK                  0x1C000000U
-#define  RESETB_WIDTH                        0x1U
-#define  RESETB_SHIFT                        0x1DU
-#define  RESETB_MASK                         0x20000000U
-
-//aonsys con
-#define AON_GP_REG_WIDTH                                   0x20U
-#define AON_GP_REG_SHIFT                                   0x0U
-#define AON_GP_REG_MASK                                    0xFFFFFFFFU
-
-
-#define M31_DPHY_REFCLK_RESERVED	0
-#define M31_DPHY_REFCLK_12M		1
-#define M31_DPHY_REFCLK_19_2M		2
-#define M31_DPHY_REFCLK_25M		3
-#define M31_DPHY_REFCLK_26M		4
-#define M31_DPHY_REFCLK_27M		5
-#define M31_DPHY_REFCLK_38_4M		6
-#define M31_DPHY_REFCLK_52M		7
-#define M31_DPHY_REFCLK_BUTT		8
-
-#define DPHY_TX_PSW_EN_MASK		(1<<30)
-
-struct m31_dphy_config {
-    int ref_clk;
-    unsigned long bitrate;
-    uint32_t pll_prev_div, pll_fbk_int, pll_fbk_fra, extd_cycle_sel;
-    uint32_t dlane_hs_pre_time, dlane_hs_zero_time, dlane_hs_trail_time;
-    uint32_t clane_hs_pre_time, clane_hs_zero_time, clane_hs_trail_time;
-    uint32_t clane_hs_clk_pre_time, clane_hs_clk_post_time;
-};
-
-#define M31_DPHY_REFCLK         M31_DPHY_REFCLK_12M
-#define M31_DPHY_BITRATE_ALIGN  10000000
-
-
-
-static const struct m31_dphy_config m31_dphy_configs[] = {
-#if (M31_DPHY_REFCLK == M31_DPHY_REFCLK_25M)
-	{25000000,  100000000, 0x1, 0x80, 0x000000, 0x4, 0x10, 0x21, 0x17, 0x07, 0x35, 0x0F, 0x0F, 0x73,},
-	{25000000,  200000000, 0x1, 0x80, 0x000000, 0x3, 0x0C, 0x1B, 0x13, 0x07, 0x35, 0x0F, 0x07, 0x3F,},
-	{25000000,  300000000, 0x1, 0xC0, 0x000000, 0x3, 0x11, 0x25, 0x19, 0x0A, 0x50, 0x15, 0x07, 0x45,},
-	{25000000,  400000000, 0x1, 0x80, 0x000000, 0x2, 0x0A, 0x18, 0x11, 0x07, 0x35, 0x0F, 0x03, 0x25,},
-	{25000000,  500000000, 0x1, 0xA0, 0x000000, 0x2, 0x0C, 0x1D, 0x14, 0x09, 0x42, 0x12, 0x03, 0x28,},
-	{25000000,  600000000, 0x1, 0xC0, 0x000000, 0x2, 0x0E, 0x23, 0x17, 0x0A, 0x50, 0x15, 0x03, 0x2B,},
-	{25000000,  700000000, 0x1, 0x70, 0x000000, 0x1, 0x08, 0x14, 0x0F, 0x06, 0x2F, 0x0E, 0x01, 0x16,},
-	{25000000,  800000000, 0x1, 0x80, 0x000000, 0x1, 0x09, 0x17, 0x10, 0x07, 0x35, 0x0F, 0x01, 0x18,},
-	{25000000,  900000000, 0x1, 0x90, 0x000000, 0x1, 0x0A, 0x19, 0x12, 0x08, 0x3C, 0x10, 0x01, 0x19,},
-	{25000000, 1000000000, 0x1, 0xA0, 0x000000, 0x1, 0x0B, 0x1C, 0x13, 0x09, 0x42, 0x12, 0x01, 0x1B,},
-	{25000000, 1100000000, 0x1, 0xB0, 0x000000, 0x1, 0x0C, 0x1E, 0x15, 0x09, 0x4A, 0x14, 0x01, 0x1D,},
-	{25000000, 1200000000, 0x1, 0xC0, 0x000000, 0x1, 0x0E, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x01, 0x1E,},
-	{25000000, 1300000000, 0x1, 0x68, 0x000000, 0x0, 0x07, 0x12, 0x0D, 0x05, 0x2C, 0x0D, 0x00, 0x0F,},
-	{25000000, 1400000000, 0x1, 0x70, 0x000000, 0x0, 0x07, 0x14, 0x0E, 0x06, 0x2F, 0x0E, 0x00, 0x10,},
-	{25000000, 1500000000, 0x1, 0x78, 0x000000, 0x0, 0x08, 0x14, 0x0F, 0x06, 0x32, 0x0E, 0x00, 0x11,},
-	{25000000, 1600000000, 0x1, 0x80, 0x000000, 0x0, 0x09, 0x15, 0x10, 0x07, 0x35, 0x0F, 0x00, 0x12,},
-	{25000000, 1700000000, 0x1, 0x88, 0x000000, 0x0, 0x09, 0x17, 0x10, 0x07, 0x39, 0x10, 0x00, 0x12,},
-	{25000000, 1800000000, 0x1, 0x90, 0x000000, 0x0, 0x0A, 0x18, 0x11, 0x08, 0x3C, 0x10, 0x00, 0x13,},
-	{25000000, 1900000000, 0x1, 0x98, 0x000000, 0x0, 0x0A, 0x1A, 0x12, 0x08, 0x3F, 0x11, 0x00, 0x14,},
-	{25000000, 2000000000, 0x1, 0xA0, 0x000000, 0x0, 0x0B, 0x1B, 0x13, 0x09, 0x42, 0x12, 0x00, 0x15,},
-	{25000000, 2100000000, 0x1, 0xA8, 0x000000, 0x0, 0x0B, 0x1C, 0x13, 0x09, 0x46, 0x13, 0x00, 0x15,},
-	{25000000, 2200000000, 0x1, 0xB0, 0x000000, 0x0, 0x0C, 0x1D, 0x14, 0x09, 0x4A, 0x14, 0x00, 0x16,},
-	{25000000, 2300000000, 0x1, 0xB8, 0x000000, 0x0, 0x0C, 0x1F, 0x15, 0x0A, 0x4C, 0x14, 0x00, 0x17,},
-	{25000000, 2400000000, 0x1, 0xC0, 0x000000, 0x0, 0x0D, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x00, 0x18,},
-	{25000000, 2500000000, 0x1, 0xC8, 0x000000, 0x0, 0x0E, 0x21, 0x16, 0x0B, 0x53, 0x16, 0x00, 0x18,},
-#elif (M31_DPHY_REFCLK == M31_DPHY_REFCLK_12M)
-     {12000000, 160000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d,},
-	{12000000, 170000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d,},
-	{12000000, 180000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e,},
-	{12000000, 190000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xc, 0x1a, 0x12, 0x6, 0x33, 0xe, 0x7, 0x3e,},
-	{12000000, 200000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x3, 0xc, 0x1b, 0x13, 0x7, 0x35, 0xf, 0x7, 0x3f,},
-	{12000000, 320000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23,},
-	{12000000, 330000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23,},
-	{12000000, 340000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23,},
-	{12000000, 350000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x9, 0x15, 0x10, 0x6, 0x2f, 0xe, 0x3, 0x24,},
-	{12000000, 360000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x2, 0x9, 0x16, 0x10, 0x6, 0x30, 0xe, 0x3, 0x24,},
-	{12000000, 370000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x17, 0x10, 0x6, 0x32, 0xe, 0x3, 0x24,},
-	{12000000, 380000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x17, 0x10, 0x6, 0x33, 0xe, 0x3, 0x24,},
-	{12000000, 390000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x17, 0x11, 0x6, 0x35, 0xf, 0x3, 0x25,},
-	{12000000, 400000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x2, 0xa, 0x18, 0x11, 0x7, 0x35, 0xf, 0x3, 0x25,},
-	{12000000, 410000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x19, 0x11, 0x7, 0x37, 0xf, 0x3, 0x25,},
-	{12000000, 420000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x19, 0x12, 0x7, 0x38, 0x10, 0x3, 0x26,},
-	{12000000, 430000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x19, 0x12, 0x7, 0x39, 0x10, 0x3, 0x26,},
-	{12000000, 440000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xb, 0x1a, 0x12, 0x7, 0x3b, 0x10, 0x3, 0x26,},
-	{12000000, 450000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x2, 0xb, 0x1b, 0x12, 0x8, 0x3c, 0x10, 0x3, 0x26,},
-	{12000000, 460000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x1b, 0x13, 0x8, 0x3d, 0x11, 0x3, 0x27,},
-	{12000000, 470000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1b, 0x13, 0x8, 0x3e, 0x11, 0x3, 0x27,},
-	{12000000, 480000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1c, 0x13, 0x8, 0x40, 0x11, 0x3, 0x27,},
-	{12000000, 490000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x2, 0xc, 0x1d, 0x14, 0x8, 0x42, 0x12, 0x3, 0x28,},
-	{12000000, 500000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28,},
-	{12000000, 510000000, 0x0, 0xaa, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28,},
-	{12000000, 520000000, 0x0, 0xad, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29,},
-	{12000000, 530000000, 0x0, 0xb0, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29,},
-	{12000000, 540000000, 0x0, 0xb4, 0x0<<16|0x0<<8|0x0, 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29,},
-	{12000000, 550000000, 0x0, 0xb7, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a,},
-	{12000000, 560000000, 0x0, 0xba, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4a, 0x14, 0x3, 0x2a,},
-	{12000000, 570000000, 0x0, 0xbe, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4c, 0x14, 0x3, 0x2a,},
-	{12000000, 580000000, 0x0, 0xc1, 0x55<<16|0x55<<8|0x55, 0x2, 0xe, 0x21, 0x16, 0xa, 0x4d, 0x14, 0x3, 0x2a,},
-	{12000000, 590000000, 0x0, 0xc4, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b,},
-	{12000000, 600000000, 0x0, 0xc8, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x23, 0x17, 0xa, 0x50, 0x15, 0x3, 0x2b,},
-	{12000000, 610000000, 0x0, 0xcb, 0x55<<16|0x55<<8|0x55, 0x2, 0xf, 0x22, 0x17, 0xb, 0x50, 0x15, 0x3, 0x2b,},
-	{12000000, 620000000, 0x0, 0xce, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xf, 0x23, 0x18, 0xb, 0x52, 0x16, 0x3, 0x2c,},
-	{12000000, 630000000, 0x0, 0x69, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x12, 0xd, 0x5, 0x2a, 0xc, 0x1, 0x15,},
-	{12000000, 640000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2b, 0xd, 0x1, 0x16,},
-	{12000000, 650000000, 0x0, 0x6c, 0x55<<16|0x55<<8|0x55, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2c, 0xd, 0x1, 0x16,},
-	{12000000, 660000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,},
-	{12000000, 670000000, 0x0, 0x6f, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,},
-	{12000000, 680000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2e, 0xd, 0x1, 0x16,},
-	{12000000, 690000000, 0x0, 0x73, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x14, 0xe, 0x6, 0x2e, 0xd, 0x1, 0x16,},
-	{12000000, 700000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x16,},
-	{12000000, 710000000, 0x0, 0x76, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x17,},
-	{12000000, 720000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x15, 0xf, 0x6, 0x30, 0xe, 0x1, 0x17,},
-	{12000000, 730000000, 0x0, 0x79, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x15, 0xf, 0x6, 0x31, 0xe, 0x1, 0x17,},
-	{12000000, 740000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x15, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,},
-	{12000000, 750000000, 0x0, 0x7d, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x16, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,},
-	{12000000, 760000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x15, 0xf, 0x6, 0x33, 0xe, 0x1, 0x17,},
-	{12000000, 770000000, 0x0, 0x80, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x15, 0x10, 0x6, 0x34, 0xf, 0x1, 0x18,},
-	{12000000, 780000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x16, 0x10, 0x6, 0x35, 0xf, 0x1, 0x18,},
-	{12000000, 790000000, 0x0, 0x83, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x16, 0x10, 0x7, 0x34, 0xf, 0x1, 0x18,},
-	{12000000, 800000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x17, 0x10, 0x7, 0x35, 0xf, 0x1, 0x18,},
-	{12000000, 810000000, 0x0, 0x87, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x17, 0x10, 0x7, 0x36, 0xf, 0x1, 0x18,},
-	{12000000, 820000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x17, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,},
-	{12000000, 830000000, 0x0, 0x8a, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x18, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,},
-	{12000000, 840000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x18, 0x11, 0x7, 0x38, 0x10, 0x1, 0x19,},
-	{12000000, 850000000, 0x0, 0x8d, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x17, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,},
-	{12000000, 860000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x18, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,},
-	{12000000, 870000000, 0x0, 0x91, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3a, 0x10, 0x1, 0x19,},
-	{12000000, 880000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3b, 0x10, 0x1, 0x19,},
-	{12000000, 890000000, 0x0, 0x94, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x19, 0x11, 0x7, 0x3c, 0x10, 0x1, 0x19,},
-	{12000000, 900000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x10, 0x1, 0x19,},
-	{12000000, 910000000, 0x0, 0x97, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x11, 0x1, 0x1a,},
-	{12000000, 920000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3d, 0x11, 0x1, 0x1a,},
-	{12000000, 930000000, 0x0, 0x9b, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,},
-	{12000000, 940000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,},
-	{12000000, 950000000, 0x0, 0x9e, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3f, 0x11, 0x1, 0x1a,},
-	{12000000, 960000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x40, 0x11, 0x1, 0x1a,},
-	{12000000, 970000000, 0x0, 0xa1, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x41, 0x12, 0x1, 0x1b,},
-	{12000000, 980000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,},
-	{12000000, 990000000, 0x0, 0xa5, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,},
-	{12000000, 1000000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1c, 0x13, 0x9, 0x42, 0x12, 0x1, 0x1b,},
-
-#endif
-};
-
-
-struct dsi_sf_priv {
-	void __iomem *dsi_reg;
-	void __iomem *phy_reg;//0x295e0000
-	void __iomem *sys_reg;
-	struct mipi_dsi_device device;
-	struct udevice *panel;
-	struct udevice *dsi_host;
-	unsigned int data_lanes;
-
-	struct clk dsi_sys_clk;
-	struct clk apb_clk;
-	struct clk txesc_clk;
-	struct clk dpi_clk;
-	struct clk dphy_txesc_clk;
-
-	struct reset_ctl dpi_rst;
-	struct reset_ctl apb_rst;
-	struct reset_ctl rxesc_rst;
-	struct reset_ctl sys_rst;
-	struct reset_ctl txbytehs_rst;
-	struct reset_ctl txesc_rst;
-	struct reset_ctl dphy_sys;
-	struct reset_ctl dphy_txbytehs;
-
-    uint32_t direct_cmd_fifo_depth;
-	uint32_t rx_fifo_depth;
-    int direct_cmd_comp;
-    bool link_initialized;
-};
-
-int rk_mipi_read_timing(struct udevice *dev,
-			       struct display_timing *timing);
-
-int rk_mipi_dsi_enable(struct udevice *dev,
-			      const struct display_timing *timing);
-
-int rk_mipi_phy_enable(struct udevice *dev);
-
-
-#endif
diff --git a/drivers/video/starfive/sf_vop.c b/drivers/video/starfive/sf_vop.c
deleted file mode 100644
index b2ad6e4c59..0000000000
--- a/drivers/video/starfive/sf_vop.c
+++ /dev/null
@@ -1,618 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- */
-
-#include <common.h>
-#include <display.h>
-#include <dm.h>
-#include <dm/uclass.h>
-#include <dm/device.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
-
-#include <regmap.h>
-#include <syscon.h>
-#include <video.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#include <power-domain-uclass.h>
-#include <power-domain.h>
-#include <clk.h>
-#include <video_bridge.h>
-#include <power/pmic.h>
-#include <panel.h>
-
-#include "sf_vop.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sf_vop_power(struct udevice *dev)
-{
-	struct udevice *dev_power;
-	struct udevice *dev_pmic;
-	struct power_domain_ops *ops;
-	struct power_domain power_domain;
-	int ret;
-	if (!(gd->flags & GD_FLG_RELOC))
-		 return 0;
-	ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
-	if (ret)
-		return ret;
-
-	ret = device_probe(dev_power);
-	if (ret) {
-		pr_err("%s: device '%s' display won't probe (ret=%d)\n",
-		   __func__, dev_power->name, ret);
-		return ret;
-	}
-
-	ops = (struct power_domain_ops *)dev_power->driver->ops;
-	power_domain.dev = dev_power;
-	power_domain.id = 4;
-	ret = ops->request(&power_domain);
-	if (ret) {
-		pr_err("ops->request() failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = ops->on(&power_domain);
-	if (ret) {
-		pr_err("ops->on() failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = uclass_get_device_by_driver(UCLASS_PMIC,
-			  DM_DRIVER_GET(pmic_starfive), &dev_pmic);
-	if (ret) {
-		pr_err("failed to find PMIC: %d\n", ret);
-		return ret;
-	}
-
-	ret = pmic_clrsetbits(dev_pmic, POWER_SW_0_REG, 0x3f, 0x3f);
-	if (ret) {
-		pr_err("failed to update SD control register: %d", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int vout_get_rst_clock_resources(struct udevice *dev)
-{
-	struct sf_vop_priv *priv = dev_get_priv(dev);
-	int ret;
-
-	ret = clk_get_by_name(dev, "disp_axi", &priv->disp_axi);
-	if (ret) {
-		pr_err("clk_get_by_name(noc_disp) failed: %d", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "vout_src", &priv->vout_src);
-	if (ret) {
-		pr_err("clk_get_by_name(vout_src) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "top_vout_axi", &priv->top_vout_axi);
-	if (ret) {
-		pr_err("clk_get_by_name(top_vout_axi) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "top_vout_ahb", &priv->top_vout_ahb);
-	if (ret) {
-		pr_err("clk_get_by_name(top_vout_ahb) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc_pix0", &priv->dc_pix0);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_pix0) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc_pix1", &priv->dc_pix1);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_pix0) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc_axi", &priv->dc_axi);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_axi) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc_core", &priv->dc_core);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_core) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc_ahb", &priv->dc_ahb);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "top_vout_lcd", &priv->top_vout_lcd);
-	if (ret) {
-		pr_err("clk_get_by_name(top_vout_lcd) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "hdmitx0_pixelclk", &priv->hdmitx0_pixelclk);
-	if (ret) {
-		pr_err("clk_get_by_name(hdmitx0_pixelclk) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc8200_pix0", &priv->dc_pix_src);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_pix_src) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc8200_pix0_out", &priv->dc_pix0_out);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_pix0_out) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = clk_get_by_name(dev, "dc8200_pix1_out", &priv->dc_pix1_out);
-	if (ret) {
-		pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = reset_get_by_name(dev, "rst_vout_src", &priv->rst_vout_src);
-	if (ret) {
-		pr_err("failed to get rst_vout_src reset (ret=%d)\n", ret);
-		return ret;
-	}
-
-	ret = reset_get_by_name(dev, "rst_axi", &priv->dc8200_rst_axi);
-	if (ret) {
-		pr_err("failed to get dc8200_rst_axi reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "rst_ahb", &priv->dc8200_rst_ahb);
-	if (ret) {
-		pr_err("failed to get ahb reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "rst_core", &priv->dc8200_rst_core);
-	if (ret) {
-		pr_err("failed to get dc8200_rst_core reset (ret=%d)\n", ret);
-		return ret;
-	}
-	ret = reset_get_by_name(dev, "rst_noc_disp", &priv->noc_disp);
-	if (ret) {
-		pr_err("failed to get noc_disp reset (ret=%d)\n", ret);
-		return ret;
-	}
-
-	debug("%s: OK\n", __func__);
-	return 0;
-}
-
-
-
-int dc_hw_init(struct udevice *dev)
-{
-	struct sf_vop_priv *priv = dev_get_priv(dev);
-
-	u32 revision = readl(priv->regs_hi+DC_HW_REVISION);
-	u32 cid = readl(priv->regs_hi+DC_HW_CHIP_CID);
-
-	debug("%s: revision = %08x\n", __func__,revision);
-	debug("%s: cid = %08x\n", __func__,cid);
-
-	return 0;
-}
-
-static int vout_probe_resources_jh7110(struct udevice *dev)
-{
-	struct sf_vop_priv *priv = dev_get_priv(dev);
-	int ret;
-	ret = vout_get_rst_clock_resources(dev);
-
-	ret = clk_enable(&priv->disp_axi);
-	if (ret < 0) {
-		pr_err("clk_enable(noc_disp) failed: %d\n", ret);
-		return ret;
-	}
-	ret = reset_deassert(&priv->noc_disp);
-	if (ret) {
-		pr_err("failed to deassert noc_disp reset (ret=%d)\n", ret);
-		goto free_clock_vout_src;
-	}
-	ret = clk_enable(&priv->vout_src);
-	if (ret < 0) {
-		pr_err("clk_enable(vout_src) failed: %d\n", ret);
-		goto free_clock_vout_src;
-	}
-	ret = clk_enable(&priv->top_vout_axi);
-	if (ret < 0) {
-		pr_err("clk_enable(top_vout_axi) failed: %d\n", ret);
-		goto free_clock_top_vout_axi;
-	}
-	ret = clk_enable(&priv->top_vout_ahb);
-	if (ret < 0) {
-		pr_err("clk_enable(top_vout_ahb) failed: %d\n", ret);
-		goto free_clock_top_vout_ahb;
-	}
-
-	ret = reset_deassert(&priv->rst_vout_src);
-	if (ret) {
-		pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
-		goto free_clock_dc_pix0;
-	}
-	ret = clk_enable(&priv->dc_pix0);
-	if (ret < 0) {
-		pr_err("clk_enable(dc_pix0) failed: %d\n", ret);
-		goto free_clock_dc_pix0;
-	}
-
-	ret = clk_enable(&priv->dc_pix1);
-	if (ret < 0) {
-		pr_err("clk_enable(dc_pix1) failed: %d\n", ret);
-		goto free_clock_dc_pix1;
-	}
-
-	ret = clk_enable(&priv->dc_axi);
-	if (ret < 0) {
-		pr_err("clk_enable(dc_axi) failed: %d\n", ret);
-		goto free_clock_dc_axi;
-	}
-
-	ret = clk_enable(&priv->dc_core);
-	if (ret < 0) {
-		pr_err("clk_enable(dc_core) failed: %d\n", ret);
-		goto free_clock_dc_core;
-	}
-
-	ret = clk_enable(&priv->dc_ahb);
-	if (ret < 0) {
-		pr_err("clk_enable(dc_ahb) failed: %d\n", ret);
-		goto free_clock_dc_ahb;
-	}
-
-	ret = clk_enable(&priv->hdmitx0_pixelclk);
-	if (ret < 0) {
-		pr_err("clk_enable(hdmitx0_pixelclk) failed: %d\n", ret);
-		goto free_clock_hdmitx0_pixelclk;
-	}
-
-	ret = reset_deassert(&priv->dc8200_rst_axi);
-	if (ret) {
-		pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
-		goto free_reset_dc8200;
-	}
-
-	ret = reset_deassert(&priv->dc8200_rst_core);
-	if (ret) {
-		pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
-		goto free_reset_dc8200;
-	}
-
-	ret = reset_deassert(&priv->dc8200_rst_ahb);
-	if (ret) {
-		pr_err("failed to deassert dc8200_rst_ahb reset (ret=%d)\n", ret);
-		goto free_reset_dc8200;
-	}
-
-	debug("%s: OK\n", __func__);
-	return 0;
-
-free_reset_dc8200:
-	clk_disable(&priv->hdmitx0_pixelclk);
-free_clock_hdmitx0_pixelclk:
-	clk_disable(&priv->dc_ahb);
-free_clock_dc_ahb:
-	clk_disable(&priv->dc_core);
-free_clock_dc_core:
-	clk_disable(&priv->dc_axi);
-free_clock_dc_axi:
-	clk_disable(&priv->dc_pix1);
-free_clock_dc_pix1:
-	clk_disable(&priv->dc_pix0);
-free_clock_dc_pix0:
-	clk_disable(&priv->top_vout_ahb);
-free_clock_top_vout_ahb:
-	clk_disable(&priv->top_vout_axi);
-free_clock_top_vout_axi:
-	clk_disable(&priv->vout_src);
-free_clock_vout_src:
-	clk_disable(&priv->disp_axi);
-
-	return ret;
-
-}
-
-static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
-{
-	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
-	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct sf_vop_priv *priv = dev_get_priv(dev);
-	int vop_id, remote_vop_id;
-	struct display_timing timing;
-	struct udevice *disp;
-	int ret;
-	u32 remote_phandle;
-	ofnode remote;
-	const char *compat;
-
-	struct udevice *panel = NULL;
-
-	ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
-	if (ret)
-		return ret;
-
-	remote = ofnode_get_by_phandle(remote_phandle);
-	if (!ofnode_valid(remote))
-		return -EINVAL;
-	remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
-	uc_priv->bpix = VIDEO_BPP32;
-
-	/*
-	 * The remote-endpoint references into a subnode of the encoder
-	 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
-	 * the following (assume 'hdmi_in_vopl' to be referenced):
-	 *
-	 * hdmi: hdmi@ff940000 {
-	 *   ports {
-	 *     hdmi_in: port {
-	 *       hdmi_in_vopb: endpoint@0 { ... };
-	 *       hdmi_in_vopl: endpoint@1 { ... };
-	 *     }
-	 *   }
-	 * }
-	 *
-	 * The original code had 3 steps of "walking the parent", but
-	 * a much better (as in: less likely to break if the DTS
-	 * changes) way of doing this is to "find the enclosing device
-	 * of UCLASS_DISPLAY".
-	 */
-	while (ofnode_valid(remote)) {
-		remote = ofnode_get_parent(remote);
-		if (!ofnode_valid(remote)) {
-			debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
-			      __func__, dev_read_name(dev));
-			return -EINVAL;
-		}
-
-		uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &disp);
-		if (disp)
-			break;
-	};
-	compat = ofnode_get_property(remote, "compatible", NULL);
-	if (!compat) {
-		printf("%s(%s): Failed to find compatible property\n",
-		      __func__, dev_read_name(dev));
-		return -EINVAL;
-	}
-	if (strstr(compat, "edp")) {
-		vop_id = VOP_MODE_EDP;
-	} else if (strstr(compat, "mipi")) {
-		vop_id = VOP_MODE_MIPI;
-	} else if (strstr(compat, "hdmi")) {
-		vop_id = VOP_MODE_HDMI;
-	} else if (strstr(compat, "cdn-dp")) {
-		vop_id = VOP_MODE_DP;
-	} else if (strstr(compat, "lvds")) {
-		vop_id = VOP_MODE_LVDS;
-	} else {
-		printf("%s(%s): Failed to find vop mode for %s\n",
-		      __func__, dev_read_name(dev), compat);
-		return -EINVAL;
-	}
-
-	ret = device_probe(disp);
-	if (ret) {
-		printf("%s: device '%s' display won't probe (ret=%d)\n",
-		      __func__, dev->name, ret);
-		return ret;
-	}
-	debug("%s,vop_id = %d\n", __func__,vop_id);
-
-	if(vop_id == VOP_MODE_MIPI)
-	{
-		ret = video_bridge_attach(disp);
-		if (ret) {
-			printf("fail to attach bridge\n");
-			return ret;
-		}
-
-		ret = video_bridge_set_backlight(disp, 80);
-		if (ret) {
-			debug("dp: failed to set backlight\n");
-			return ret;
-		}
-
-		ret = uclass_first_device_err(UCLASS_PANEL, &panel);
-		if (ret) {
-			if (ret != -ENODEV)
-				printf("panel device error %d\n", ret);
-			return ret;
-		}
-
-		ret = panel_get_display_timing(panel, &timing);
-		if (ret) {
-			ret = ofnode_decode_display_timing(dev_ofnode(panel),
-							   0, &timing);
-			if (ret) {
-				printf("decode display timing error %d\n", ret);
-				return ret;
-			}
-		}
-
-		int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
-		if (err) {
-			printf("failed to set %s clock as %s's parent\n",
-				priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
-			return err;
-		}
-
-		ulong new_rate = clk_set_rate(&priv->dc_pix_src, timing.pixelclock.typ);
-		debug("new_rate  %ld\n", new_rate);
-
-		dc_hw_init(dev);
-
-		uc_priv->xsize = timing.hactive.typ;
-		uc_priv->ysize = timing.vactive.typ;
-
-		if (IS_ENABLED(CONFIG_VIDEO_COPY))
-			uc_plat->copy_base = uc_plat->base - uc_plat->size / 2;
-
-		writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
-		writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
-		writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
-		writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
-		writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
-		writel(uc_plat->base, priv->regs_hi+0x00001400);
-		writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
-		writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
-		writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
-		writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
-		writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
-		writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
-		writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
-		writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
-		writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
-		writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
-		writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
-		writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
-		writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
-		writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
-		writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
-		writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
-		writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
-		writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
-		writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
-		writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
-		writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
-		writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
-		writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
-		writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
-		writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
-		writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
-		writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
-		writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
-		writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
-		writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
-		writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
-		writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
-		writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
-		writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
-		writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
-		writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
-		writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
-		writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
-	}
-
-	return 0;
-}
-
-static int sf_vop_probe(struct udevice *dev)
-{
-	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-	struct sf_vop_priv *priv = dev_get_priv(dev);
-
-	ofnode port, node;
-	int ret;
-
-	sf_vop_power(dev);
-	mdelay(50);
-
-	priv->regs_hi = dev_remap_addr_name(dev, "hi");
-	if (!priv->regs_hi)
-		return -EINVAL;
-
-	priv->regs_low = dev_remap_addr_name(dev, "low");
-	if (!priv->regs_low)
-		return -EINVAL;
-
-	vout_probe_resources_jh7110(dev);
-
-	/*
-	 * Try all the ports until we find one that works. In practice this
-	 * tries EDP first if available, then HDMI.
-	 *
-	 * Note that rockchip_vop_set_clk() always uses NPLL as the source
-	 * clock so it is currently not possible to use more than one display
-	 * device simultaneously.
-	 */
-	port = dev_read_subnode(dev, "port");
-	if (!ofnode_valid(port)) {
-		debug("%s(%s): 'port' subnode not found\n",
-		      __func__, dev_read_name(dev));
-		return -EINVAL;
-	}
-
-	for (node = ofnode_first_subnode(port);
-	     ofnode_valid(node);
-	     node = dev_read_next_subnode(node)) {
-		ret = sf_display_init(dev, plat->base, node);
-		if (ret)
-			debug("Device failed: ret=%d\n", ret);
-		if (!ret)
-			break;
-	}
-
-	video_set_flush_dcache(dev, 1);
-
-	return 0;
-}
-
-static int sf_vop_remove(struct udevice *dev)
-{
-	return 0;
-}
-
-struct rkvop_driverdata rk3288_driverdata = {
-	.features = VOP_FEATURE_OUTPUT_10BIT,
-};
-
-static const struct udevice_id sf_dc_ids[] = {
-	{ .compatible = "starfive,sf-dc8200",
-	  .data = (ulong)&rk3288_driverdata },
-	{ }
-};
-
-static const struct video_ops sf_vop_ops = {
-};
-
-int sf_vop_bind(struct udevice *dev)
-{
-	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-
-	plat->size = 4 * (CONFIG_VIDEO_STARFIVE_MAX_XRES *
-			  CONFIG_VIDEO_STARFIVE_MAX_YRES);
-	printf("%s,%d,plat->size = %d\n",__func__,__LINE__,plat->size);
-
-	return 0;
-}
-
-U_BOOT_DRIVER(starfive_dc8200) = {
-	.name	= "starfive_dc8200",
-	.id	= UCLASS_VIDEO,
-	.of_match = sf_dc_ids,
-	.ops	= &sf_vop_ops,
-	.bind	= sf_vop_bind,
-	.probe	= sf_vop_probe,
-    .remove = sf_vop_remove,
-	.priv_auto	= sizeof(struct sf_vop_priv),
-};
diff --git a/drivers/video/starfive/sf_vop.h b/drivers/video/starfive/sf_vop.h
deleted file mode 100644
index 6d3e572f62..0000000000
--- a/drivers/video/starfive/sf_vop.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#ifndef __RK_VOP_H__
-#define __RK_VOP_H__
-#include <clk.h>
-#include <reset.h>
-
-#define AQ_INTR_ACKNOWLEDGE				0x0010
-#define AQ_INTR_ENBL					0x0014
-#define DC_HW_REVISION					0x0024
-#define DC_HW_CHIP_CID					0x0030
-
-#define DC_REG_BASE						0x0800
-#define DC_REG_RANGE					0x2000
-#define DC_SEC_REG_OFFSET				0x100000
-
- //define power management i2c cmd(reg+data)
-#define POWER_SW_0_REG                           (0x00+0x80)
-#define POWER_SW_0_VDD18_HDMI                    0
-#define POWER_SW_0_VDD18_MIPITX                  1
-#define POWER_SW_0_VDD18_MIPIRX                  2
-#define POWER_SW_0_VDD09_HDMI                    3
-#define POWER_SW_0_VDD09_MIPITX                  4
-#define POWER_SW_0_VDD09_MIPIRX                  5
-
-enum vop_modes {
-	VOP_MODE_EDP = 0,
-	VOP_MODE_MIPI,
-	VOP_MODE_HDMI,
-	VOP_MODE_LVDS,
-	VOP_MODE_DP,
-};
-
-struct sf_vop_priv {
-	void __iomem * regs_hi;
-	void __iomem * regs_low;
-	struct udevice *conn_dev;
-	struct display_timing timings;
-
-	struct clk disp_axi;
-	struct clk vout_src;
-	struct clk top_vout_axi;
-	struct clk top_vout_ahb;
-
-	struct clk dc_pix0;
-	struct clk dc_pix1;
-	struct clk dc_axi;
-	struct clk dc_core;
-	struct clk dc_ahb;
-
-	struct clk top_vout_lcd;
-	struct clk hdmitx0_pixelclk;
-	struct clk dc_pix_src;
-	struct clk dc_pix0_out;
-	struct clk dc_pix1_out;
-
-	struct reset_ctl vout_resets;
-
-//20221014
-	struct reset_ctl dc8200_rst_axi;
-	struct reset_ctl dc8200_rst_core;
-	struct reset_ctl dc8200_rst_ahb;
-
-	struct reset_ctl rst_vout_src;
-	struct reset_ctl noc_disp;
-};
-
-enum vop_features {
-	VOP_FEATURE_OUTPUT_10BIT = (1 << 0),
-};
-
-struct rkvop_driverdata {
-	/* configuration */
-	u32 features;
-	/* block-specific setters/getters */
-	void (*set_pin_polarity)(struct udevice *, enum vop_modes, u32);
-};
-
-/**
- * rk_vop_probe() - common probe implementation
- *
- * Performs the rk_display_init on each port-subnode until finding a
- * working port (or returning an error if none of the ports could be
- * successfully initialised).
- *
- * @dev:	device
- * @return 0 if OK, -ve if something went wrong
- */
-int rk_vop_probe(struct udevice *dev);
-
-/**
- * rk_vop_bind() - common bind implementation
- *
- * Sets the plat->size field to the amount of memory to be reserved for
- * the framebuffer: this is always
- *     (32 BPP) x VIDEO_ROCKCHIP_MAX_XRES x VIDEO_ROCKCHIP_MAX_YRES
- *
- * @dev:	device
- * @return 0 (always OK)
- */
-int rk_vop_bind(struct udevice *dev);
-
-/**
- * rk_vop_probe_regulators() - probe (autoset + enable) regulators
- *
- * Probes a list of regulators by performing autoset and enable
- * operations on them.  The list of regulators is an array of string
- * pointers and any individual regulator-probe may fail without
- * counting as an error.
- *
- * @dev:	device
- * @names:	array of string-pointers to regulator names to probe
- * @cnt:	number of elements in the 'names' array
- */
-void rk_vop_probe_regulators(struct udevice *dev,
-			     const char * const *names, int cnt);
-
-#endif
diff --git a/drivers/video/starfive/voutpmic.h b/drivers/video/starfive/voutpmic.h
deleted file mode 100644
index cadca0f1ce..0000000000
--- a/drivers/video/starfive/voutpmic.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#define PMIC_JH7110_51MCU_I2C_SLAVE_REG_BASE            0x80
-#define PMIC_JH7110_51MCU_I2C_SLAVE_REG_END             0x90
-#define POWER_SW_0_REG                                  (0x00+PMIC_JH7110_51MCU_I2C_SLAVE_REG_BASE)
-#define POWER_SW_0_VDD18_HDMI                           0
-#define POWER_SW_0_VDD18_MIPITX                         1
-#define POWER_SW_0_VDD18_MIPIRX                         2
-#define POWER_SW_0_VDD09_HDMI                           3
-#define POWER_SW_0_VDD09_MIPITX                         4
-#define POWER_SW_0_VDD09_MIPIRX                         5
-#define POWER_SW_1_REG                                  (0x01+PMIC_JH7110_51MCU_I2C_SLAVE_REG_BASE)
-#define POWER_SW_1_VDD1833_SD0_18                       0
-#define BIT(x)                                          (1UL<<(x))
-
-typedef enum {
-    PMU_DOMAIN_SYSTOP                   = BIT(0),
-    PMU_DOMAIN_CPU                      = BIT(1),
-    PMU_DOMAIN_GPUA                     = BIT(2),
-    PMU_DOMAIN_VDEC                     = BIT(3),
-    PMU_DOMAIN_VOUT                     = BIT(4),
-    PMU_DOMAIN_ISP                      = BIT(5),
-    PMU_DOMAIN_VENC                     = BIT(6),
-    PMU_DOMAIN_ALL                      = (PMU_DOMAIN_SYSTOP|PMU_DOMAIN_CPU|PMU_DOMAIN_GPUA|PMU_DOMAIN_VDEC \
-                                              |PMU_DOMAIN_VOUT|PMU_DOMAIN_ISP|PMU_DOMAIN_VENC),
-    PMU_DOMAIN_PMIC_VDD18_HDMI          = BIT(16),
-    PMU_DOMAIN_PMIC_VDD18_MIPITX        = BIT(17),
-    PMU_DOMAIN_PMIC_VDD18_MIPIRX        = BIT(18),
-    PMU_DOMAIN_PMIC_VDD09_HDMI          = BIT(19),
-    PMU_DOMAIN_PMIC_VDD09_MIPITX        = BIT(20),
-    PMU_DOMAIN_PMIC_VDD09_MIPIRX        = BIT(21),
-    PMU_DOMAIN_PMIC_VDD1833_SD0_18      = BIT(22),
-    PMU_DOMAIN_PMIC_ALL                 = (PMU_DOMAIN_PMIC_VDD18_HDMI|PMU_DOMAIN_PMIC_VDD18_MIPITX|PMU_DOMAIN_PMIC_VDD18_MIPIRX \
-                                            |PMU_DOMAIN_PMIC_VDD09_HDMI|PMU_DOMAIN_PMIC_VDD09_MIPITX|PMU_DOMAIN_PMIC_VDD09_MIPIRX \
-                                            |PMU_DOMAIN_PMIC_VDD1833_SD0_18),
-} sys_pmu_domain_t;
-
-enum pmic_domain {
-    PMIC_DOMAIN_0       = 0,
-    PMIC_DOMAIN_1       = 1,
-    PMIC_DOMAIN_2       = 2,
-    PMIC_DOMAIN_3       = 3,
-    PMIC_DOMAIN_4       = 4,
-    PMIC_DOMAIN_5       = 5,
-    PMIC_DOMAIN_6       = 6,
-    PMIC_DOMAIN_7       = 7,
-    PMIC_DOMAIN_8       = 8,
-    PMIC_DOMAIN_9       = 9,
-    PMIC_DOMAIN_10      = 10,
-    PMIC_DOMAIN_11      = 11,
-    PMIC_DOMAIN_12      = 12,
-    PMIC_DOMAIN_13      = 13,
-    PMIC_DOMAIN_14      = 14,
-    PMIC_DOMAIN_15      = 15,
-};
-
-static struct {
-    int pmu_dom;
-    int pmic_dom;
-} pmu_pmic_table[] = {
-    { PMU_DOMAIN_PMIC_VDD18_HDMI,        PMIC_DOMAIN_0 },
-    { PMU_DOMAIN_PMIC_VDD18_MIPITX,      PMIC_DOMAIN_1 },
-    { PMU_DOMAIN_PMIC_VDD18_MIPIRX,      PMIC_DOMAIN_2 },
-    { PMU_DOMAIN_PMIC_VDD09_HDMI,        PMIC_DOMAIN_3 },
-    { PMU_DOMAIN_PMIC_VDD09_MIPITX,      PMIC_DOMAIN_4 },
-    { PMU_DOMAIN_PMIC_VDD09_MIPIRX,      PMIC_DOMAIN_5 },
-    { PMU_DOMAIN_PMIC_VDD1833_SD0_18,    PMIC_DOMAIN_6 },
-};
-
-enum pmic_switch {
-    PMIC_SWITCH_OFF,
-    PMIC_SWITCH_ON,
-};
\ No newline at end of file
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 52a1d94743..9f8cf6ef2a 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -192,8 +192,7 @@ int video_sync(struct udevice *vid, bool force)
 	 * architectures do not actually implement it. Is there a way to find
 	 * out whether it exists? For now, ARM is safe.
 	 */
-#if (defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) || defined(CONFIG_RISCV)
-
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	struct video_priv *priv = dev_get_uclass_priv(vid);
 
 	if (priv->flush_dcache) {
@@ -265,7 +264,7 @@ int video_sync_copy(struct udevice *dev, void *from, void *to)
 		 * frame buffer
 		 */
 		if (offset < -priv->fb_size || offset > 2 * priv->fb_size) {
-#if DEBUG
+#ifdef DEBUG
 			char str[80];
 
 			snprintf(str, sizeof(str),