diff options
author | Tom Rini <trini@konsulko.com> | 2020-04-07 18:58:44 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2020-04-08 00:13:35 +0300 |
commit | 1f47e2aca42c2e51ff3a7754c717ee13f568c721 (patch) | |
tree | eca6cb5e551dbb75c2328b1dba3e7a2b8a77d327 /drivers/serial/ns16550.c | |
parent | 2b18b89156335bf1f0d84f81d3597762bc48c61d (diff) | |
parent | 895a7866c20cf6c01779b5a60fbf2770b88930a4 (diff) | |
download | u-boot-1f47e2aca42c2e51ff3a7754c717ee13f568c721.tar.xz |
Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.07
common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code
xilinx:
- Enable netconsole
Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE
Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver
ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3
Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR
Drivers:
- Gem:
- Flush memory after freeing
- Handle mdio bus separately
- Watchdog:
- Get rid of unused global data pointer
- Enable window watchdog timer
- Serial:
- Change reinitialization logic in zynq serial driver
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/serial/ns16550.c')
-rw-r--r-- | drivers/serial/ns16550.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c1b303ffcb..a2f1b35629 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -479,39 +479,38 @@ static int ns16550_serial_getinfo(struct udevice *dev, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) -static int ns1655_serial_set_base_addr(struct udevice *dev) +static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base) { - fdt_addr_t addr; - struct ns16550_platdata *plat; - - plat = dev_get_platdata(dev); - - addr = dev_read_addr_pci(dev); - if (addr == FDT_ADDR_T_NONE) + if (base == FDT_ADDR_T_NONE) return -EINVAL; #ifdef CONFIG_SYS_NS16550_PORT_MAPPED - plat->base = addr; + plat->base = base; #else - plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); #endif return 0; } -#endif int ns16550_serial_probe(struct udevice *dev) { + struct ns16550_platdata *plat = dev->platdata; struct NS16550 *const com_port = dev_get_priv(dev); struct reset_ctl_bulk reset_bulk; + fdt_addr_t addr; int ret; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = ns1655_serial_set_base_addr(dev); - if (ret) - return ret; -#endif + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, assign platdata->base before probing hardware. + */ + if (device_is_on_pci_bus(dev)) { + addr = devfdt_get_addr_pci(dev); + ret = ns16550_serial_assign_base(plat, addr); + if (ret) + return ret; + } ret = reset_get_bulk(dev, &reset_bulk); if (!ret) @@ -535,9 +534,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; const u32 port_type = dev_get_driver_data(dev); + fdt_addr_t addr; struct clk clk; int err; + addr = dev_read_addr(dev); + err = ns16550_serial_assign_base(plat, addr); + if (err && !device_is_on_pci_bus(dev)) + return err; + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); |