diff options
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-07 13:50:09 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-24 08:21:06 +0300 |
| commit | 6c4b50e6deb719726a04ca154a6361bd866398f5 (patch) | |
| tree | 8ccc2d154642e6b2e3f3a3b76a93e6957f495904 /arch/riscv | |
| parent | 005f9627d02e8ecab3c58c77889060e72f7fa25d (diff) | |
| download | u-boot-6c4b50e6deb719726a04ca154a6361bd866398f5.tar.xz | |
riscv: dts: jh7110: Add clock source from PLL
Change the PLL clock source from syscrg to sys_syscon child node.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 | ||||
| -rw-r--r-- | arch/riscv/dts/jh7110-u-boot.dtsi | 1 | ||||
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 8 |
3 files changed, 9 insertions, 6 deletions
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index 710b082766..b90e7f8995 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -313,9 +313,9 @@ <&syscrg JH7110_SYSCLK_BUS_ROOT>, <&syscrg JH7110_SYSCLK_PERH_ROOT>, <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>, - <&syscrg JH7110_SYSCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_PLL2_OUT>, + assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, + <&pllclk JH7110_SYSCLK_PLL2_OUT>, + <&pllclk JH7110_SYSCLK_PLL2_OUT>, <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; assigned-clock-rates = <0>, <0>, <0>, <0>; }; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index c22119518c..2f560e7296 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -83,7 +83,6 @@ &syscrg { bootph-pre-ram; - starfive,sys-syscon = <&sys_syscon>; }; &stgcrg { diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 7a8141a8e9..825fbb7198 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -487,12 +487,16 @@ <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_SYSCLK_PLL0_OUT>, + <&pllclk JH7110_SYSCLK_PLL1_OUT>, + <&pllclk JH7110_SYSCLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; |