diff options
author | Hal Feng <hal.feng@starfivetech.com> | 2022-01-13 10:31:14 +0300 |
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committer | Tekkaman Ninja <tekkamanninja@163.com> | 2022-02-15 12:48:26 +0300 |
commit | ef571fcead40632331f5441836e27161cb776a17 (patch) | |
tree | 2ed1dd7e7bf0d8bf23db04baa42d7d4fed80d485 /arch/riscv/dts/jh7100.dtsi | |
parent | ca3cac173d7f1d046c44894f7f27a444f103fbe2 (diff) | |
download | u-boot-ef571fcead40632331f5441836e27161cb776a17.tar.xz |
riscv: dts: starfive: add watchdog nodeSDK_v2.1.0
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'arch/riscv/dts/jh7100.dtsi')
-rw-r--r-- | arch/riscv/dts/jh7100.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi index 953b35e099..7489b53ea8 100644 --- a/arch/riscv/dts/jh7100.dtsi +++ b/arch/riscv/dts/jh7100.dtsi @@ -136,6 +136,20 @@ reg-names = "control"; }; + wdog: wdog@12480000 { + compatible = "starfive,si5-wdt"; + reg = <0x0 0x12480000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <80>; + interrupt-names = "wdog"; + clocks = <&clkgen JH7100_CLK_WDT_CORE>, + <&clkgen JH7100_CLK_WDTIMER_APB>; + clock-names = "core_clk", "apb_clk"; + clock-frequency = <50000000>; + timeout-sec = <15>; + status = "okay"; + }; + plic: interrupt-controller@c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; |