diff options
author | Bin Meng <bin.meng@windriver.com> | 2021-01-31 15:35:57 +0300 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2021-02-03 13:38:41 +0300 |
commit | 85c714d8dcd56f63c2c0ae1b0f6a7e4a96c918a4 (patch) | |
tree | 2d185c829f6461849cfbf6d5988233d013506afe /arch/riscv/cpu/fu540/dram.c | |
parent | 7a3c628c43f7200684edf81783e11b69fd0fd7df (diff) | |
download | u-boot-85c714d8dcd56f63c2c0ae1b0f6a7e4a96c918a4.tar.xz |
riscv: Adjust board_get_usable_ram_top() for 32-bit
When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().
While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
board_get_usable_ram_top() can be updated to cover both 64-bit
and 32-bit RISC-V.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv/cpu/fu540/dram.c')
-rw-r--r-- | arch/riscv/cpu/fu540/dram.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 1dc77efeca..259da65a54 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -22,7 +22,6 @@ int dram_init_banksize(void) ulong board_get_usable_ram_top(ulong total_size) { -#ifdef CONFIG_64BIT /* * Ensure that we run from first 4GB so that all * addresses used by U-Boot are 32bit addresses. @@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size) * devices work fine because DMA mapping APIs will * provide 32bit DMA addresses only. */ - if (gd->ram_top > SZ_4G) - return SZ_4G; -#endif + if (gd->ram_top >= SZ_4G) + return SZ_4G - 1; + return gd->ram_top; } |