diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-11-07 18:08:54 +0300 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-12-17 07:58:01 +0300 |
| commit | 2f27754eb7f5321b9e4ff80870f03e35357a02a5 (patch) | |
| tree | 088bcd09aadd3d257242696bfedbeefbebe99cb8 /arch/arm/mach-socfpga/spl_a10.c | |
| parent | 5b20efeafec0ebe0ee5742c611e4f2153346797a (diff) | |
| download | u-boot-2f27754eb7f5321b9e4ff80870f03e35357a02a5.tar.xz | |
arm: socfpga: arria10: Setting image magic value to romcode initswstate reg
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/spl_a10.c')
| -rw-r--r-- | arch/arm/mach-socfpga/spl_a10.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index ecb656e4de..f6c4b5708d 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2019 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2021 Altera Corporation <www.altera.com> */ #include <common.h> @@ -32,6 +32,7 @@ #include <memalign.h> #define FPGA_BUFSIZ 16 * 1024 +#define FSBL_IMAGE_IS_VALID 0x49535756 DECLARE_GLOBAL_DATA_PTR; @@ -169,3 +170,10 @@ void board_init_f(ulong dummy) config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); } + +/* board specific function prior loading SSBL / U-Boot proper */ +void spl_board_prepare_for_boot(void) +{ + writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + + SYSMGR_A10_ROMCODE_INITSWSTATE); +} |