diff options
| author | Marek Vasut <marex@denx.de> | 2018-08-06 23:07:40 +0300 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-08-13 23:35:42 +0300 |
| commit | ccc97432adf50156da86132ad75e3a99c9c0d3eb (patch) | |
| tree | 0677a1998c4697e1662fc7ec28ffb87fcb39482f /arch/arm/dts/socfpga_arria10_socdk.dtsi | |
| parent | f4c3e0dcf5be525b7db3c46f1dd111663181a03a (diff) | |
| download | u-boot-ccc97432adf50156da86132ad75e3a99c9c0d3eb.tar.xz | |
ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/dts/socfpga_arria10_socdk.dtsi')
| -rw-r--r-- | arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 4018a5b929..9160c20bd0 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -167,3 +167,28 @@ &watchdog1 { status = "okay"; }; + +/* Clock available early */ +&main_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&main_periph_ref_clk { + u-boot,dm-pre-reloc; +}; + +&peri_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&noc_free_clk { + u-boot,dm-pre-reloc; +}; + +&l4_mp_clk { + u-boot,dm-pre-reloc; +}; + +&l4_sp_clk { + u-boot,dm-pre-reloc; +}; |