arm: armada: dts: Use a single dtsi for cp110 die description

Use a single dtsi file for CP110 die instead of master/slave.
Moving to single file will allow miltiple DTSI inclusions with
re-defined CP index and name.
This change will also allow support for SoCs containing more than
two CP110 dies on board.
Move pin control definitions from CP110 DTS to board DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 36 insertions, 36 deletions

diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 720c95082b..86df6ac0b2 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -15,9 +15,9 @@
 	};
 
 	aliases {
-		i2c0 = &cpm_i2c0;
-		i2c1 = &cpm_i2c1;
-		spi0 = &cps_spi1;
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		spi0 = &cp1_spi1;
 	};
 
 	memory@00000000 {
@@ -31,14 +31,14 @@
 		reg_usb3h0_vbus: usb3-vbus0 {
 			compatible = "regulator-fixed";
 			pinctrl-names = "default";
-			pinctrl-0 = <&cpm_xhci_vbus_pins>;
+			pinctrl-0 = <&cp0_xhci_vbus_pins>;
 			regulator-name = "reg-usb3h0-vbus";
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			startup-delay-us = <300000>;
 			shutdown-delay-us = <500000>;
 			regulator-force-boot-off;
-			gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
+			gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
 		};
 	};
 };
@@ -66,7 +66,7 @@
 	status = "okay";
 };
 
-&cpm_pinctl {
+&cp0_pinctl {
 	/*
 	 * MPP Bus:
 	 * [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -99,57 +99,57 @@
 		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
 		     0xe  0xe  0 >;
 
-	cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
 		marvell,pins = < 32 >;
 		marvell,function = <0>;
 	};
 
-	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+	cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
 		marvell,pins = < 47 >;
 		marvell,function = <0>;
 	};
 
-	cps_1g_phy_reset: cps-1g-phy-reset {
+	cp1_1g_phy_reset: cp1-1g-phy-reset {
 		marvell,pins = < 43 >;
 		marvell,function = <0>;
 	};
 };
 
 /* uSD slot */
-&cpm_sdhci0 {
+&cp0_sdhci0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cpm_sdhci_pins>;
+	pinctrl-0 = <&cp0_sdhci_pins>;
 	bus-width = <4>;
 	status = "okay";
 };
 
-&cpm_pcie0 {
+&cp0_pcie0 {
 	num-lanes = <1>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&cpm_pcie_reset_pins>;
-	marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&cp0_pcie_reset_pins>;
+	marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
-&cpm_i2c0 {
+&cp0_i2c0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cpm_i2c0_pins>;
+	pinctrl-0 = <&cp0_i2c0_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 };
 
-&cpm_i2c1 {
+&cp0_i2c1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cpm_i2c1_pins>;
+	pinctrl-0 = <&cp0_i2c1_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 };
 
-&cpm_sata0 {
+&cp0_sata0 {
 	status = "okay";
 };
 
-&cpm_comphy {
+&cp0_comphy {
 	/*
 	 * CP0 Serdes Configuration:
 	 * Lane 0: PCIe0 (x1)
@@ -179,31 +179,31 @@
 	};
 };
 
-&cpm_ethernet {
+&cp0_ethernet {
         pinctrl-names = "default";
         status = "okay";
 };
 
 /* 10G SFI SFP */
-&cpm_eth0 {
+&cp0_eth0 {
         status = "okay";
         phy-mode = "sfi";
 };
 
-&cps_sata0 {
+&cp1_sata0 {
 	status = "okay";
 };
 
-&cps_usb3_0 {
+&cp1_usb3_0 {
 	vbus-supply = <&reg_usb3h0_vbus>;
 	status = "okay";
 };
 
-&cps_utmi0 {
+&cp1_utmi0 {
 	status = "okay";
 };
 
-&cps_pinctl {
+&cp1_pinctl {
 	/*
 	 * MPP Bus:
 	 * [0-5] TDM
@@ -234,9 +234,9 @@
 		     0xff 0xff 0xff>;
 };
 
-&cps_spi1 {
+&cp1_spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cps_spi1_pins>;
+	pinctrl-0 = <&cp1_spi1_pins>;
 	status = "okay";
 
 	spi-flash@0 {
@@ -261,7 +261,7 @@
 	};
 };
 
-&cps_comphy {
+&cp1_comphy {
 	/*
 	 * CP1 Serdes Configuration:
 	 * Lane 0: SATA 1 (RX swapped). Can be PCIe0
@@ -294,30 +294,30 @@
 	};
 };
 
-&cps_mdio {
+&cp1_mdio {
 	phy0: ethernet-phy@0 {
 		reg = <0>;
 	};
 };
 
-&cps_ethernet {
+&cp1_ethernet {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cps_1g_phy_reset>;
+	pinctrl-0 = <&cp1_1g_phy_reset>;
 	status = "okay";
 };
 
 /* 1G SGMII */
-&cps_eth1 {
+&cp1_eth1 {
 	status = "okay";
 	phy-mode = "sgmii";
 	phy = <&phy0>;
-	phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>;
+	phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
 };
 
 /* 2.5G to Topaz switch */
-&cps_eth2 {
+&cp1_eth2 {
 	status = "okay";
 	phy-mode = "sgmii";
 	phy-speed = <2500>;
-	phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>;
+	phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>;
 };