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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-04-29 08:59:41 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-05-03 06:04:03 +0300 |
| commit | a8de36a40f9b518e85accdde6c180c5576d168f2 (patch) | |
| tree | b76bfc2d4f78bc0eaae603cf45f2ad50fd43540c | |
| parent | af8c4f6366308350f7eedf6bd4e1bc15a32c6b39 (diff) | |
| download | u-boot-a8de36a40f9b518e85accdde6c180c5576d168f2.tar.xz | |
riscv: dts: dubhe: Add Dubhe *-u-boot.dtsi
Move dubhe-fpga-u-boot.dtsi to dubhe_fpga_common-u-boot.dtsi and add
dubhe*-u-boot.dtsi
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rw-r--r-- | arch/riscv/dts/dubhe70_fpga-u-boot.dtsi | 20 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe80_fpga-u-boot.dtsi | 20 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe90_fpga-u-boot.dtsi | 20 | ||||
| -rw-r--r-- | arch/riscv/dts/dubhe_fpga_common-u-boot.dtsi (renamed from arch/riscv/dts/dubhe-fpga-u-boot.dtsi) | 28 |
4 files changed, 87 insertions, 1 deletions
diff --git a/arch/riscv/dts/dubhe70_fpga-u-boot.dtsi b/arch/riscv/dts/dubhe70_fpga-u-boot.dtsi new file mode 100644 index 0000000000..6e069b5801 --- /dev/null +++ b/arch/riscv/dts/dubhe70_fpga-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +#include "dubhe_fpga_common-u-boot.dtsi" + +&cpu0 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu1 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu2 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu3 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; diff --git a/arch/riscv/dts/dubhe80_fpga-u-boot.dtsi b/arch/riscv/dts/dubhe80_fpga-u-boot.dtsi new file mode 100644 index 0000000000..6e069b5801 --- /dev/null +++ b/arch/riscv/dts/dubhe80_fpga-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +#include "dubhe_fpga_common-u-boot.dtsi" + +&cpu0 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu1 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu2 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; + +&cpu3 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_sscofpmf_svinval_svnapot_svpbmt"; +}; diff --git a/arch/riscv/dts/dubhe90_fpga-u-boot.dtsi b/arch/riscv/dts/dubhe90_fpga-u-boot.dtsi new file mode 100644 index 0000000000..7c634bdc92 --- /dev/null +++ b/arch/riscv/dts/dubhe90_fpga-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +#include "dubhe_fpga_common-u-boot.dtsi" + +&cpu0 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; +}; + +&cpu1 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; +}; + +&cpu2 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; +}; + +&cpu3 { + riscv,isa = "rv64imafdch_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; +}; diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe_fpga_common-u-boot.dtsi index 382a940edc..dc912d6394 100644 --- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi +++ b/arch/riscv/dts/dubhe_fpga_common-u-boot.dtsi @@ -2,6 +2,11 @@ /* Copyright (c) 2021 StarFive Technology Co., Ltd. */ / { + + aliases { + spi0 = &qspi1; + }; + chosen { stdout-path = "serial0"; bootph-pre-ram; @@ -21,6 +26,14 @@ cpu@1 { bootph-pre-ram; }; + + cpu@2 { + bootph-pre-ram; + }; + + cpu@3 { + bootph-pre-ram; + }; }; memory@80000000 { @@ -157,7 +170,7 @@ &spi0 { bootph-pre-ram; - + mmc@0 { bootph-pre-ram; }; @@ -182,3 +195,16 @@ &cpu0_intc { bootph-pre-ram; }; + +&cpu1_intc { + bootph-pre-ram; +}; + +&cpu2_intc { + bootph-pre-ram; +}; + +&cpu3_intc { + bootph-pre-ram; +}; + |