Merge branch 'dubhe_fpga_dev_v2023.10-add-binman-support' into 'dubhe_fpga_dev_v2023.10'

arch: riscv: dts: dubhe: Add Dubhe-90/80/70 device tree

See merge request starfive-tech/u-boot!76

13 files changed, 354 insertions, 47 deletions

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f829340756..a831ed00be 100755
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -10,8 +10,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
 dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
 include $(srctree)/scripts/Makefile.dts
-dtb-$(CONFIG_TARGET_STARFIVE_DUBHE_FPGA) += dubhe_fpga.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_DUBHE_FPGA) += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb
+dtb-$(CONFIG_TARGET_STARFIVE_DUBHE_FPGA) += dubhe90_fpga.dtb dubhe80_fpga.dtb dubhe70_fpga.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
index bc853c54f5..95e0dc3f26 100644
--- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
+++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
@@ -39,6 +39,103 @@
 			bootph-pre-ram;
 		};
 	};
+
+	binman: binman	{
+		multiple-images;
+
+		uboot_fit {
+			filename = "u-boot.itb";
+
+			fit {
+				description = "Configuration to load OpenSBI before U-Boot";
+				#address-cells = <1>;
+				fit,fdt-list = "of-list";
+
+				images {
+					uboot {
+						description = "U-Boot";
+						type = "standalone";
+						os = "U-Boot";
+						arch = "riscv";
+						compression = "none";
+						load = <CONFIG_TEXT_BASE>;
+
+						uboot_blob: blob-ext {
+							filename = "u-boot-nodtb.bin";
+						};
+					};
+
+					opensbi {
+						description = "OpenSBI fw_dynamic Firmware";
+						type = "firmware";
+						os = "opensbi";
+						arch = "riscv";
+						compression = "none";
+						load = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+						entry = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+
+						opensbi_blob: opensbi {
+							filename = "fw_dynamic.bin";
+						};
+					};
+
+					fdt-90 {
+						description = "U-Boot proper device tree binary";
+						type = "flat_dt";
+						arch = "riscv";
+						compression = "none";
+						fdt_90_blob: blob-ext {
+							filename = "arch/riscv/dts/dubhe90_fpga.dtb";
+						};
+					};
+
+					fdt-80 {
+						description = "U-Boot proper device tree binary";
+						type = "flat_dt";
+						arch = "riscv";
+						compression = "none";
+						fdt_80_blob: blob-ext {
+							filename = "arch/riscv/dts/dubhe80_fpga.dtb";
+						};
+					};
+
+					fdt-70 {
+						description = "U-Boot proper device tree binary";
+						type = "flat_dt";
+						arch = "riscv";
+						compression = "none";
+						fdt_70_blob: blob-ext {
+							filename = "arch/riscv/dts/dubhe70_fpga.dtb";
+						};
+					};
+				};
+
+				configurations {
+					default = "conf-90";
+					conf-90 {
+						description = "conf-90";
+						firmware = "opensbi";
+						loadables = "uboot";
+						fdt = "fdt-90";
+					};
+
+					conf-80 {
+						description = "conf-80";
+						firmware = "opensbi";
+						loadables = "uboot";
+						fdt = "fdt-80";
+					};
+
+					conf-70 {
+						description = "conf-70";
+						firmware = "opensbi";
+						loadables = "uboot";
+						fdt = "fdt-70";
+					};
+				};
+			};
+		};
+	};
 };
 
 &clint {
diff --git a/arch/riscv/dts/dubhe.dtsi b/arch/riscv/dts/dubhe.dtsi
index 5f3df5681c..7037a93735 100644
--- a/arch/riscv/dts/dubhe.dtsi
+++ b/arch/riscv/dts/dubhe.dtsi
@@ -41,6 +41,72 @@
 				interrupt-controller;
 			};
 		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		l2_cache0: cache-controller-0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-unified;
+		};
+
+		l2_cache1: cache-controller-1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	pmu {
+		compatible = "riscv,pmu";
+		interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>;
+		riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+					   <0x00006 0x0000 0xB>,
+					   <0x00008 0x0000 0x10>,
+					   <0x00009 0x0000 0xF>,
+					   <0x10000 0x0000 0x19>,
+					   <0x10001 0x0000 0x1A>,
+					   <0x10002 0x0000 0x1B>,
+					   <0x10003 0x0000 0x1C>,
+					   <0x10008 0x0000 0x8>,
+					   <0x10009 0x0000 0x9>,
+					   <0x1000C 0x0000 0x9E>,
+					   <0x1000D 0x0000 0x9F>,
+					   <0x10010 0x0000 0x1D>,
+					   <0x10011 0x0000 0x1E>,
+					   <0x10012 0x0000 0x1F>,
+					   <0x10013 0x0000 0x20>,
+					   <0x10014 0x0000 0x21>,
+					   <0x10018 0x0000 0x17>,
+					   <0x10019 0x0000 0x18>,
+					   <0x10020 0x0000 0x8>,
+					   <0x10021 0x0000 0x7>;
+
+		riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+					      <0x00008 0x00009 0x00007FF8>,
+					      <0x10000 0x10003 0x00007FF8>,
+					      <0x10008 0x10009 0x00007FF8>,
+					      <0x1000C 0x1000D 0x00007FF8>,
+					      <0x10010 0x10014 0x00007FF8>,
+					      <0x10018 0x10019 0x00007FF8>,
+					      <0x10020 0x10021 0x00007FF8>;
+
+		riscv,raw-event-to-mhpmcounters =
+			<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
+			<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
+			<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */
 	};
 
 	soc {
@@ -146,46 +212,5 @@
 			snps,rxpbl = <4>;
 			status = "disabled";
 		};
-
-		pmu {
-			compatible = "riscv,pmu";
-			interrupts-extended = <&cpu0_intc 13>,
-				<&cpu1_intc 13>;
-			riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
-				<0x00006 0x0000 0xB>,
-				<0x00008 0x0000 0x10>,
-				<0x00009 0x0000 0xF>,
-				<0x10000 0x0000 0x19>,
-				<0x10001 0x0000 0x1A>,
-				<0x10002 0x0000 0x1B>,
-				<0x10003 0x0000 0x1C>,
-				<0x10008 0x0000 0x8>,
-				<0x10009 0x0000 0x9>,
-				<0x1000C 0x0000 0x9E>,
-				<0x1000D 0x0000 0x9F>,
-				<0x10010 0x0000 0x1D>,
-				<0x10011 0x0000 0x1E>,
-				<0x10012 0x0000 0x1F>,
-				<0x10013 0x0000 0x20>,
-				<0x10014 0x0000 0x21>,
-				<0x10018 0x0000 0x17>,
-				<0x10019 0x0000 0x18>,
-				<0x10020 0x0000 0x8>,
-				<0x10021 0x0000 0x7>;
-
-			riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
-				<0x00008 0x00009 0x00007FF8>,
-				<0x10000 0x10003 0x00007FF8>,
-				<0x10008 0x10009 0x00007FF8>,
-				<0x1000C 0x1000D 0x00007FF8>,
-				<0x10010 0x10014 0x00007FF8>,
-				<0x10018 0x10019 0x00007FF8>,
-				<0x10020 0x10021 0x00007FF8>;
-
-			riscv,raw-event-to-mhpmcounters =
-				<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
-				<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
-				<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */
-		};
 	};
 };
diff --git a/arch/riscv/dts/dubhe70.dtsi b/arch/riscv/dts/dubhe70.dtsi
new file mode 100644
index 0000000000..58928c1895
--- /dev/null
+++ b/arch/riscv/dts/dubhe70.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 StarFive Technology Co., Ltd. */
+
+#include "dubhe.dtsi"
+
+&cpu0 {
+	compatible = "starfive,dubhe-70", "riscv";
+	riscv,isa = "rv64imafdcbh_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf";
+	riscv,cbom-block-size = <64>;
+	riscv,cboz-block-size = <64>;
+	d-cache-block-size = <64>;
+	d-cache-sets = <512>;
+	d-cache-size = <32768>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <16>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <512>;
+	i-cache-size = <32768>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <24>;
+	next-level-cache = <&l2_cache0>;
+};
+
+&cpu1 {
+	compatible = "starfive,dubhe-70", "riscv";
+	riscv,isa = "rv64imafdcbh_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf";
+	riscv,cbom-block-size = <64>;
+	riscv,cboz-block-size = <64>;
+	d-cache-block-size = <64>;
+	d-cache-sets = <512>;
+	d-cache-size = <32768>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <16>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <512>;
+	i-cache-size = <32768>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <24>;
+	next-level-cache = <&l2_cache1>;
+
+};
+
+&l2_cache0 {
+	cache-sets = <2048>;
+	cache-size = <0x20000>;
+};
+
+&l2_cache1 {
+	cache-sets = <2048>;
+	cache-size = <0x20000>;
+};
diff --git a/arch/riscv/dts/dubhe70_fpga.dts b/arch/riscv/dts/dubhe70_fpga.dts
new file mode 100644
index 0000000000..a4e9ea608c
--- /dev/null
+++ b/arch/riscv/dts/dubhe70_fpga.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 StarFive Technology Co., Ltd. */
+
+#include "dubhe70.dtsi"
+#include "dubhe_fpga_common.dtsi"
diff --git a/arch/riscv/dts/dubhe80.dtsi b/arch/riscv/dts/dubhe80.dtsi
new file mode 100644
index 0000000000..2206d4d71e
--- /dev/null
+++ b/arch/riscv/dts/dubhe80.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 StarFive Technology Co., Ltd. */
+
+#include "dubhe.dtsi"
+
+&cpu0 {
+	compatible = "starfive,dubhe-80", "riscv";
+	d-cache-block-size = <64>;
+	d-cache-sets = <512>;
+	d-cache-size = <32768>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <48>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <512>;
+	i-cache-size = <32768>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <48>;
+	next-level-cache = <&l2_cache0>;
+};
+
+&cpu1 {
+	compatible = "starfive,dubhe-80", "riscv";
+	d-cache-block-size = <64>;
+	d-cache-sets = <512>;
+	d-cache-size = <32768>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <48>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <512>;
+	i-cache-size = <32768>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <48>;
+	next-level-cache = <&l2_cache1>;
+};
+
+&l2_cache0 {
+	cache-sets = <512>;
+	cache-size = <0x40000>;
+};
+
+&l2_cache1 {
+	cache-sets = <512>;
+	cache-size = <0x40000>;
+};
diff --git a/arch/riscv/dts/dubhe80_fpga.dts b/arch/riscv/dts/dubhe80_fpga.dts
new file mode 100644
index 0000000000..5248de0ae3
--- /dev/null
+++ b/arch/riscv/dts/dubhe80_fpga.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 StarFive Technology Co., Ltd. */
+
+#include "dubhe80.dtsi"
+#include "dubhe_fpga_common.dtsi"
diff --git a/arch/riscv/dts/dubhe90.dtsi b/arch/riscv/dts/dubhe90.dtsi
new file mode 100644
index 0000000000..3a4535f449
--- /dev/null
+++ b/arch/riscv/dts/dubhe90.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+#include "dubhe.dtsi"
+
+&cpu0 {
+	compatible = "starfive,dubhe-90", "riscv";
+	d-cache-block-size = <64>;
+	d-cache-sets = <1024>;
+	d-cache-size = <65536>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <48>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <1024>;
+	i-cache-size = <65536>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <48>;
+	next-level-cache = <&l2_cache0>;
+};
+
+&cpu1 {
+	compatible = "starfive,dubhe-90", "riscv";
+	d-cache-block-size = <64>;
+	d-cache-sets = <1024>;
+	d-cache-size = <65536>;
+	d-tlb-sets = <1>;
+	d-tlb-size = <48>;
+	i-cache-block-size = <64>;
+	i-cache-sets = <1024>;
+	i-cache-size = <65536>;
+	i-tlb-sets = <1>;
+	i-tlb-size = <48>;
+	next-level-cache = <&l2_cache0>;
+};
+
+&l2_cache0 {
+	cache-sets = <4096>;
+	cache-size = <0x200000>;
+};
+
+/delete-node/ &l2_cache1;
diff --git a/arch/riscv/dts/dubhe90_fpga.dts b/arch/riscv/dts/dubhe90_fpga.dts
new file mode 100644
index 0000000000..5f9f266165
--- /dev/null
+++ b/arch/riscv/dts/dubhe90_fpga.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+#include "dubhe90.dtsi"
+#include "dubhe_fpga_common.dtsi"
diff --git a/arch/riscv/dts/dubhe_fpga.dts b/arch/riscv/dts/dubhe_fpga_common.dtsi
index a98bb658f4..9398205dd3 100644
--- a/arch/riscv/dts/dubhe_fpga.dts
+++ b/arch/riscv/dts/dubhe_fpga_common.dtsi
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
 
-#include "dubhe.dtsi"
-#include "binman.dtsi"
 #include "dubhe-fpga-u-boot.dtsi"
 
 / {
diff --git a/arch/riscv/include/asm/arch-dubhe/csr.h b/arch/riscv/include/asm/arch-dubhe/csr.h
new file mode 100644
index 0000000000..cf9eca495c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-dubhe/csr.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#ifndef _ASM_DUBHE_CSR_H
+#define _ASM_DUBHE_CSR_H
+
+#define CSR_MARCHID	0xf12
+#define DUBHE90_MARCHID	0xdb000090
+#define DUBHE80_MARCHID	0xdb000080
+#define DUBHE70_MARCHID	0xdb000070
+
+#endif /* _ASM_DUBHE_CSR_H */
diff --git a/board/starfive/dubhe_fpga/dubhe_fpga_spl.c b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
index 53e7c6b33e..859e54afcc 100755
--- a/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
+++ b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c
@@ -3,6 +3,8 @@
 
 #include <dm.h>
 #include <spl.h>
+#include <asm/csr.h>
+#include <asm/arch-dubhe/csr.h>
 
 int spl_board_init_f(void)
 {
@@ -26,5 +28,25 @@ void board_boot_order(u32 *spl_boot_list)
 
 int board_fit_config_name_match(const char *name)
 {
-	return 0;
+	char config_name[8];
+	u32 marchid;
+
+	marchid = csr_read(CSR_MARCHID);
+
+	switch (marchid) {
+	case DUBHE90_MARCHID:
+		sprintf(config_name, "conf-%s", "90");
+		return strcmp(name, config_name);
+
+	case DUBHE80_MARCHID:
+		sprintf(config_name, "conf-%s", "80");
+		return strcmp(name, config_name);
+
+	case DUBHE70_MARCHID:
+		sprintf(config_name, "conf-%s", "70");
+		return strcmp(name, config_name);
+
+	default:
+		return 0;
+	}
 }
diff --git a/configs/starfive_dubhe_fpga_defconfig b/configs/starfive_dubhe_fpga_defconfig
index 16268e8460..06b75a2a92 100644
--- a/configs/starfive_dubhe_fpga_defconfig
+++ b/configs/starfive_dubhe_fpga_defconfig
@@ -2,7 +2,8 @@ CONFIG_RISCV=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="dubhe_fpga"
+CONFIG_DEFAULT_DEVICE_TREE="dubhe90_fpga"
+CONFIG_OF_LIST="dubhe90_fpga dubhe80_fpga dubhe70_fpga"
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y