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authorJi Sheng Teoh <jisheng.teoh@starfivetech.com>2024-04-05 05:48:40 +0300
committerJi Sheng Teoh <jisheng.teoh@starfivetech.com>2024-04-05 06:16:04 +0300
commit6de70a3d4632366bea1a006e9f929a4e6dd7d10d (patch)
treedfa8f8ab86356a11c61ec4ee679d56077b9e2cb8
parent8af5f41224dcb2473c7d6779e6e7e4492e47394a (diff)
downloadu-boot-6de70a3d4632366bea1a006e9f929a4e6dd7d10d.tar.xz
riscv: dts: dubhe: Add root node compatible string
Some fdt matching callback function relies on the root node compatible string instead of the cpu node compatible string to enable platform specific features. Add root node compatible string in each Dubhe SoC level dtsi to clearly distinguish them. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
-rw-r--r--arch/riscv/dts/dubhe70.dtsi4
-rw-r--r--arch/riscv/dts/dubhe80.dtsi4
-rw-r--r--arch/riscv/dts/dubhe90.dtsi4
3 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/dts/dubhe70.dtsi b/arch/riscv/dts/dubhe70.dtsi
index 58928c1895..416eeefa3f 100644
--- a/arch/riscv/dts/dubhe70.dtsi
+++ b/arch/riscv/dts/dubhe70.dtsi
@@ -3,6 +3,10 @@
#include "dubhe.dtsi"
+/ {
+ compatible = "starfive,dubhe-70";
+};
+
&cpu0 {
compatible = "starfive,dubhe-70", "riscv";
riscv,isa = "rv64imafdcbh_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf";
diff --git a/arch/riscv/dts/dubhe80.dtsi b/arch/riscv/dts/dubhe80.dtsi
index 2206d4d71e..ad50c88dd3 100644
--- a/arch/riscv/dts/dubhe80.dtsi
+++ b/arch/riscv/dts/dubhe80.dtsi
@@ -3,6 +3,10 @@
#include "dubhe.dtsi"
+/ {
+ compatible = "starfive,dubhe-80";
+};
+
&cpu0 {
compatible = "starfive,dubhe-80", "riscv";
d-cache-block-size = <64>;
diff --git a/arch/riscv/dts/dubhe90.dtsi b/arch/riscv/dts/dubhe90.dtsi
index 3a4535f449..1bfd3380a8 100644
--- a/arch/riscv/dts/dubhe90.dtsi
+++ b/arch/riscv/dts/dubhe90.dtsi
@@ -3,6 +3,10 @@
#include "dubhe.dtsi"
+/ {
+ compatible = "starfive,dubhe-90";
+};
+
&cpu0 {
compatible = "starfive,dubhe-90", "riscv";
d-cache-block-size = <64>;