diff options
author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-04-29 08:33:44 +0300 |
---|---|---|
committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-05-03 06:03:56 +0300 |
commit | 4d0de3e4e50b4d67fee5d920cb5ec10b2666db15 (patch) | |
tree | 7800f6caa648d9a691b2ff61dab4d5e5e0fa63db | |
parent | 1b88f1ed0b652e4f12dc189222acf86ad6f3166d (diff) | |
download | u-boot-4d0de3e4e50b4d67fee5d920cb5ec10b2666db15.tar.xz |
riscv: dts: dubhe: Sync device tree from Linux
Sync device tree from Linux (commit 699004da6bab)
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
-rw-r--r-- | arch/riscv/dts/dubhe-fpga-u-boot.dtsi | 10 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe.dtsi | 89 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe70-cpus.dtsi | 197 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe70.dtsi | 50 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe70_fpga.dts | 7 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe80-cpus.dtsi | 169 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe80.dtsi | 43 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe90-cpus.dtsi | 158 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe90.dtsi | 40 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe_fpga_common.dtsi | 64 |
10 files changed, 600 insertions, 227 deletions
diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi index 95e0dc3f26..382a940edc 100644 --- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi +++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi @@ -139,9 +139,14 @@ }; &clint { + clocks = <&pbus_clk>; bootph-pre-ram; }; +&gmac0 { + mac-address = [de ad be ef de ad]; +}; + &pbus_clk { bootph-pre-ram; }; @@ -174,11 +179,6 @@ bootph-pre-ram; }; -&clint { - clocks = <&pbus_clk>; - bootph-pre-ram; -}; - &cpu0_intc { bootph-pre-ram; }; diff --git a/arch/riscv/dts/dubhe.dtsi b/arch/riscv/dts/dubhe.dtsi index 7037a93735..168ca7bd31 100644 --- a/arch/riscv/dts/dubhe.dtsi +++ b/arch/riscv/dts/dubhe.dtsi @@ -8,70 +8,10 @@ #size-cells = <2>; compatible = "starfive,dubhe"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "starfive,dubhe", "riscv"; - device_type = "cpu"; - mmu-type = "riscv,sv48"; - reg = <0x0>; - riscv,isa = "rv64imafdcbh_sscofpmf"; - tlb-split; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu1: cpu@1 { - compatible = "starfive,dubhe", "riscv"; - device_type = "cpu"; - mmu-type = "riscv,sv48"; - reg = <0x1>; - riscv,isa = "rv64imafdcbh_sscofpmf"; - tlb-split; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - }; - - l2_cache0: cache-controller-0 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-unified; - }; - - l2_cache1: cache-controller-1 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-unified; - }; - }; - pmu { compatible = "riscv,pmu"; - interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>; + interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>, + <&cpu2_intc 13>, <&cpu3_intc 13>; riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>, <0x00006 0x0000 0xB>, <0x00008 0x0000 0x10>, @@ -123,7 +63,11 @@ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, - <&cpu1_intc 7>; + <&cpu1_intc 7>, + <&cpu2_intc 3>, + <&cpu2_intc 7>, + <&cpu3_intc 3>, + <&cpu3_intc 7>; }; pbus_clk: subsystem_pbus_clock { @@ -137,13 +81,16 @@ #interrupt-cells = <1>; compatible = "riscv,plic0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,max-priority = <15>; riscv,ndev = <25>; interrupt-controller; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu1_intc 11>, - <&cpu1_intc 9>; + <&cpu1_intc 9>, + <&cpu2_intc 11>, + <&cpu2_intc 9>, + <&cpu3_intc 11>, + <&cpu3_intc 9>; }; spi0: spi@10000000 { @@ -184,22 +131,20 @@ snps,blen = <256 128 64 32 0 0 0>; }; - gmac0: gmac0@10100000 { - compatible = "starfive,dubhe-eqos-5.20"; + gmac0: gmac@10100000 { + compatible = "starfive,dubhe-dwmac","snps,dwmac-5.20"; reg = <0x0 0x10100000 0x0 0x10000>; clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", - "pclk", - "gtxc"; + "pclk"; interrupt-parent = <&plic0>; - interrupts = <8>, <11>, <12> ; + interrupts = <8>, <11>, <12>; interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; max-frame-size = <1500>; - phy-mode = "rgmii-id"; snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <128>; + snps,perfect-filter-entries = <8>; rx-fifo-depth = <2048>; tx-fifo-depth = <2048>; snps,fixed-burst; diff --git a/arch/riscv/dts/dubhe70-cpus.dtsi b/arch/riscv/dts/dubhe70-cpus.dtsi new file mode 100644 index 0000000000..c24cdf356e --- /dev/null +++ b/arch/riscv/dts/dubhe70-cpus.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-70", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x0>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-70", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x1>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; + next-level-cache = <&l2_cache1>; + tlb-split; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-70", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x2>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; + next-level-cache = <&l2_cache2>; + tlb-split; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-70", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x3>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; + next-level-cache = <&l2_cache3>; + tlb-split; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <0x20000>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <0x20000>; + cache-unified; + }; + + l2_cache2: cache-controller-2 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <0x20000>; + cache-unified; + }; + + l2_cache3: cache-controller-3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <0x20000>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/dts/dubhe70.dtsi b/arch/riscv/dts/dubhe70.dtsi index 416eeefa3f..8543086c11 100644 --- a/arch/riscv/dts/dubhe70.dtsi +++ b/arch/riscv/dts/dubhe70.dtsi @@ -1,55 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2023 StarFive Technology Co., Ltd. */ +/* Copyright (c) 2023-2024 StarFive Technology Co., Ltd. */ #include "dubhe.dtsi" +#include "dubhe70-cpus.dtsi" / { compatible = "starfive,dubhe-70"; }; - -&cpu0 { - compatible = "starfive,dubhe-70", "riscv"; - riscv,isa = "rv64imafdcbh_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; - riscv,cbom-block-size = <64>; - riscv,cboz-block-size = <64>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <16>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <24>; - next-level-cache = <&l2_cache0>; -}; - -&cpu1 { - compatible = "starfive,dubhe-70", "riscv"; - riscv,isa = "rv64imafdcbh_zba_zbb_zbc_zbs_zicntr_zicsr_zifencei_zihintpause_zihpm_sscofpmf"; - riscv,cbom-block-size = <64>; - riscv,cboz-block-size = <64>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <16>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <24>; - next-level-cache = <&l2_cache1>; - -}; - -&l2_cache0 { - cache-sets = <2048>; - cache-size = <0x20000>; -}; - -&l2_cache1 { - cache-sets = <2048>; - cache-size = <0x20000>; -}; diff --git a/arch/riscv/dts/dubhe70_fpga.dts b/arch/riscv/dts/dubhe70_fpga.dts index a4e9ea608c..15cc7f3715 100644 --- a/arch/riscv/dts/dubhe70_fpga.dts +++ b/arch/riscv/dts/dubhe70_fpga.dts @@ -3,3 +3,10 @@ #include "dubhe70.dtsi" #include "dubhe_fpga_common.dtsi" + +/ { + soc { + /delete-property/ dma-noncoherent; + dma-coherent; + }; +}; diff --git a/arch/riscv/dts/dubhe80-cpus.dtsi b/arch/riscv/dts/dubhe80-cpus.dtsi new file mode 100644 index 0000000000..5861b48844 --- /dev/null +++ b/arch/riscv/dts/dubhe80-cpus.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x0>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x1>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x2>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-80", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x3>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <0x100000>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/dts/dubhe80.dtsi b/arch/riscv/dts/dubhe80.dtsi index ad50c88dd3..4f1f8b03ad 100644 --- a/arch/riscv/dts/dubhe80.dtsi +++ b/arch/riscv/dts/dubhe80.dtsi @@ -1,48 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2023 StarFive Technology Co., Ltd. */ +/* Copyright (c) 2023-2024 StarFive Technology Co., Ltd. */ #include "dubhe.dtsi" +#include "dubhe80-cpus.dtsi" / { compatible = "starfive,dubhe-80"; }; - -&cpu0 { - compatible = "starfive,dubhe-80", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <48>; - next-level-cache = <&l2_cache0>; -}; - -&cpu1 { - compatible = "starfive,dubhe-80", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <48>; - next-level-cache = <&l2_cache1>; -}; - -&l2_cache0 { - cache-sets = <512>; - cache-size = <0x40000>; -}; - -&l2_cache1 { - cache-sets = <512>; - cache-size = <0x40000>; -}; diff --git a/arch/riscv/dts/dubhe90-cpus.dtsi b/arch/riscv/dts/dubhe90-cpus.dtsi new file mode 100644 index 0000000000..5833740d0e --- /dev/null +++ b/arch/riscv/dts/dubhe90-cpus.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2024 StarFive Technology Co., Ltd. */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-90", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x0>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm", "sscofpmf"; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-90", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x1>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm", "sscofpmf"; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-90", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x2>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm", "sscofpmf"; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-90", "riscv"; + device_type = "cpu"; + mmu-type = "riscv,sv48"; + reg = <0x3>; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm", "sscofpmf"; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + next-level-cache = <&l2_cache0>; + tlb-split; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible = "starfive,dubhe-l2cache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <4096>; + cache-size = <0x200000>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/dts/dubhe90.dtsi b/arch/riscv/dts/dubhe90.dtsi index 1bfd3380a8..1daec53ea8 100644 --- a/arch/riscv/dts/dubhe90.dtsi +++ b/arch/riscv/dts/dubhe90.dtsi @@ -1,45 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ +/* Copyright (c) 2021-2024 StarFive Technology Co., Ltd. */ #include "dubhe.dtsi" +#include "dubhe90-cpus.dtsi" / { compatible = "starfive,dubhe-90"; }; - -&cpu0 { - compatible = "starfive,dubhe-90", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <1024>; - d-cache-size = <65536>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <1024>; - i-cache-size = <65536>; - i-tlb-sets = <1>; - i-tlb-size = <48>; - next-level-cache = <&l2_cache0>; -}; - -&cpu1 { - compatible = "starfive,dubhe-90", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <1024>; - d-cache-size = <65536>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <1024>; - i-cache-size = <65536>; - i-tlb-sets = <1>; - i-tlb-size = <48>; - next-level-cache = <&l2_cache0>; -}; - -&l2_cache0 { - cache-sets = <4096>; - cache-size = <0x200000>; -}; - -/delete-node/ &l2_cache1; diff --git a/arch/riscv/dts/dubhe_fpga_common.dtsi b/arch/riscv/dts/dubhe_fpga_common.dtsi index 9398205dd3..13e4bcf604 100644 --- a/arch/riscv/dts/dubhe_fpga_common.dtsi +++ b/arch/riscv/dts/dubhe_fpga_common.dtsi @@ -1,14 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2021 StarFive Technology Co., Ltd. */ -#include "dubhe-fpga-u-boot.dtsi" - / { model = "StarFive Dubhe FPGA"; aliases { + ethernet0 = &gmac0; serial0 = &uart0; - spi0 = &qspi1; }; chosen { @@ -26,6 +24,7 @@ }; soc { + fpga_2p5mhz_clk: fpga_2p5mhz_clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -38,21 +37,36 @@ clock-frequency = <50000000>; }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma-reserved@260000000 { + reg = <0x2 0x60000000 0x0 0x20000000>; + no-map; + }; + + linux,dma@660000000 { + compatible = "shared-dma-pool"; + reg = <0x6 0x60000000 0x0 0x20000000>; + no-map; + linux,dma-default; + }; + }; + }; &gmac0 { status = "okay"; phy-mode = "rgmii-id"; - mac-address = [de ad be ef de ad]; - // clk_csr = <3>; - // max-speed = <10>; phy-handle = <ðernet_phy0>; clocks = <&fpga_2p5mhz_clk>, <&fpga_2p5mhz_clk>, <&fpga_2p5mhz_clk>, <&fpga_50mhz_clk>, - <&fpga_50mhz_clk>, - <&fpga_2p5mhz_clk>; + <&fpga_50mhz_clk>; mdio0 { compatible = "snps,dwmac-mdio"; @@ -61,6 +75,11 @@ ethernet_phy0: ethernet-phy@0 { reg = <0>; max-speed = <10>; + device_type = "ethernet-phy"; + marvell,reg-init = + <0x0 0x4 0 0x0441>, /*Page 0, Reg 4 <- 0x0441*/ + <0x12 0x14 0 0x0>, /*Page 18, Reg 20 <- 0x0*/ + <0x0 0x0 0 0x1100>; /*Page 0, Reg 0 <- 0x1100*/ }; }; }; @@ -80,32 +99,32 @@ status = "okay"; flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - m25p,fast-read; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - - partitions { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + m25p,fast-read; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { - reg = <0x000000 0x1000>; + reg = <0x00000000 0x00001000>; label = "Boot Copier"; - /*read-only;*/ + read-only; }; partition@1000 { - reg = <0x1000 0x1000>; + reg = <0x00001000 0x00001000>; label = "Boot Jump Code"; - /*read-only;*/ + read-only; }; partition@2000 { - reg = <0x2000 0x40000>; + reg = <0x00002000 0x00040000>; label = "U-Boot SPL"; }; @@ -119,8 +138,7 @@ label = "User"; }; }; - }; - + }; }; &uart0 { |