Merge branch 'CR_2709_pinctrl_jianlong' into 'jh7110-master'

CR_2709 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions

See merge request sdk/u-boot!18

13 files changed, 1518 insertions, 28 deletions

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 6ab4f48107..0188f89780 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -505,7 +505,7 @@
 		};
 
 		gpio: gpio@13040000 {
-			compatible = "starfive_jh7110-sys-pinctrl";
+			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
 			reg-names = "control";
 			interrupts = <91>;
@@ -516,7 +516,7 @@
 		};
 
 		gpioa: gpio@17020000 {
-			compatible = "starfive_jh7110-aon-pinctrl";
+			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
 			reg-names = "control";
 			interrupts = <90>;
diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts
index 24dc4d9a6e..1a7b48e684 100644
--- a/arch/riscv/dts/starfive_evb.dts
+++ b/arch/riscv/dts/starfive_evb.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -46,14 +47,68 @@
 		"stg_apb", "gmac0_rmii_refin";
 };
 
+&gpio {
+	status = "okay";
+
+	usb_pins: usb-pins {
+		drive-vbus-pin {
+			pinmux = <GPIOMUX(33, GPOUT_SYS_USB_DRIVE_VBUS,
+						GPOEN_ENABLE, GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		overcurrent-pin {
+			pinmux = <GPIOMUX(34, GPOUT_LOW,
+						GPOEN_DISABLE, GPI_SYS_USB_OVERCURRENT)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	mmc0_pins: mmc0-pins {
+		 mmc0-pins-rest {
+			pinmux = <GPIOMUX(22, GPOUT_SYS_SDIO0_RST,
+						GPOEN_ENABLE, GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	mmc1_pins: mmc1-pins {
+		 mmc1-pins-rest {
+			pinmux = <GPIOMUX(24, GPOUT_SYS_SDIO1_RST,
+						GPOEN_ENABLE, GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &sdio0 {
 	fifo-depth = <32>;
 	bus-width = <4>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
 };
 
 &sdio1 {
 	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
 };
 
 &gmac0 {
@@ -81,11 +136,6 @@
 	};
 };
 
-&gpio {
-	compatible = "starfive,jh7110-gpio";
-	gpio-controller;
-};
-
 &uart0 {
 	reg-offset = <0>;
 	current-speed = <115200>;
@@ -102,6 +152,8 @@
 
 &usbdrd_cdns3 {
 	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_pins>;
 };
 
 &timer {
diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c
index 95b09f7126..1dd722ef40 100644
--- a/board/starfive/evb/starfive_evb.c
+++ b/board/starfive/evb/starfive_evb.c
@@ -170,14 +170,6 @@ static void jh7110_usb_init(bool usb2_enable)
 			PDRSTN_SPLIT_MASK,
 			(0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
 	}
-	SYS_IOMUX_DOEN(33, LOW);
-	SYS_IOMUX_DOUT(33, 7);
-	SYS_IOMUX_DOEN(34, HIGH);
-
-	clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32,
-		IOMUX_USB_MASK,
-		((34+2) << IOMUX_USB_SHIFT) & IOMUX_USB_MASK);
-
 }
 
 static u32 get_chip_type(void)
@@ -198,17 +190,6 @@ static u32 get_chip_type(void)
 	return value;
 }
 
-static void jh7110_mmc_init(int id)
-{
-	if (id == 0) {
-		SYS_IOMUX_DOEN(22, LOW);
-		SYS_IOMUX_DOUT(22, 19);
-	} else {
-		SYS_IOMUX_DOEN(24, LOW);
-		SYS_IOMUX_DOUT(24, 66);
-	}
-}
-
 /*enable U74-mc hart1~hart4 prefetcher*/
 static void enable_prefetcher(void)
 {
@@ -237,8 +218,6 @@ int board_init(void)
 
 	jh7110_timer_init();
 	jh7110_usb_init(true);
-	jh7110_mmc_init(0);
-	jh7110_mmc_init(1);
 
 	return 0;
 }
diff --git a/configs/starfive_evb_defconfig b/configs/starfive_evb_defconfig
index b2afe2fb7c..12835be67a 100644
--- a/configs/starfive_evb_defconfig
+++ b/configs/starfive_evb_defconfig
@@ -92,5 +92,9 @@ CONFIG_USB_CDNS3_HOST=y
 CONFIG_USB_CDNS3_STARFIVE=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_STARFIVE=y
+CONFIG_PINCTRL_STARFIVE_JH7110=y
 # CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2 is not set
 # CONFIG_EFI_LOAD_FILE2_INITRD is not set
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 30eaa376c8..fa841a5278 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -313,5 +313,6 @@ source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 05b71f2f13..3e8b3936df 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_PINCTRL_STI)	+= pinctrl-sti.o
 obj-$(CONFIG_PINCTRL_STM32)	+= pinctrl_stm32.o
 obj-$(CONFIG_$(SPL_)PINCTRL_STMFX)	+= pinctrl-stmfx.o
 obj-y				+= broadcom/
+obj-$(CONFIG_PINCTRL_STARFIVE)	+= starfive/
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
new file mode 100644
index 0000000000..4a3afadec3
--- /dev/null
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_STARFIVE
+	bool "Pinctrl driver for StarFive SoC"
+	depends on PINCTRL_FULL
+	help
+	  Say yes here to support pin control on the StarFive RISC-V SoC.
+	  This also provides an interface to the GPIO pins not used by other
+	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
+	  and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JH7110
+	bool "Pinctrl and GPIO driver for StarFive JH7110 SoC"
+	depends on  PINCTRL_STARFIVE
+	help
+	  This selects the pinctrl driver for JH7110 starfive.
+
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
new file mode 100644
index 0000000000..2eac219d36
--- /dev/null
+++ b/drivers/pinctrl/starfive/Makefile
@@ -0,0 +1,9 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7110)	+= pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o
+
+
+
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
new file mode 100755
index 0000000000..fd606d83ff
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_AON_NGPIO		4
+#define JH7110_AON_GC_BASE		64
+
+/* registers */
+#define JH7110_AON_DOEN			0x0
+#define JH7110_AON_DOUT			0x4
+#define JH7110_AON_GPI			0x8
+#define JH7110_AON_GPIOIN		0x2c
+
+#define JH7110_AON_GPIOEN		0xc
+#define JH7110_AON_GPIOIS		0x10
+#define JH7110_AON_GPIOIC		0x14
+#define JH7110_AON_GPIOIBE		0x18
+#define JH7110_AON_GPIOIEV		0x1c
+#define JH7110_AON_GPIOIE		0x20
+#define JH7110_AON_GPIORIS		0x28
+#define JH7110_AON_GPIOMIS		0x28
+
+#define AON_GPO_PDA_0_5_CFG		0x30
+
+static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+		unsigned int din, u32 dout, u32 doen, u32 func)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+	if (pin < priv->info->ngpios && func == 0)
+		starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+	return 0;
+}
+
+static int jh7110_aon_get_padcfg_base(struct udevice *dev,
+		unsigned int pin)
+{
+	if (pin < PAD_GMAC0_MDC)
+		return AON_GPO_PDA_0_5_CFG;
+
+	return -1;
+}
+
+static void jh7110_aon_init_hw(struct udevice *dev)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+	/* mask all GPIO interrupts */
+	writel(0, priv->base + JH7110_AON_GPIOIE);
+	/* clear edge interrupt flags */
+	writel(0, priv->base + JH7110_AON_GPIOIC);
+	writel(0x0f, priv->base + JH7110_AON_GPIOIC);
+	/* enable GPIO interrupts */
+	writel(1, priv->base + JH7110_AON_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = {
+	/* pin conf */
+	.set_one_pinmux = jh7110_aon_set_one_pin_mux,
+	.get_padcfg_base  = jh7110_aon_get_padcfg_base,
+
+	/* gpio dout/doen/din/gpioinput register */
+	.dout_reg_base = JH7110_AON_DOUT,
+	.dout_mask = GENMASK(3, 0),
+	.doen_reg_base = JH7110_AON_DOEN,
+	.doen_mask = GENMASK(2, 0),
+	.gpi_reg_base = JH7110_AON_GPI,
+	.gpi_mask = GENMASK(3, 0),
+	.gpioin_reg_base = JH7110_AON_GPIOIN,
+
+	/* gpio */
+	.gpio_bank_name = "RGPIO",
+	.ngpios = JH7110_AON_NGPIO,
+	.gpio_init_hw = jh7110_aon_init_hw,
+};
+
+static int jh7110_aon_pinctrl_probe(struct udevice *dev)
+{
+	struct starfive_pinctrl_soc_info *info =
+		(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+	return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_aon_pinctrl_ids[] = {
+	/* JH7110 aon pinctrl */
+	{ .compatible = "starfive,jh7110-aon-pinctrl",
+	  .data = (ulong)&jh7110_aon_pinctrl_info, },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_aon_pinctrl) = {
+	.name		= "jh7110-aon-pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= jh7110_aon_pinctrl_ids,
+	.priv_auto	= sizeof(struct starfive_pinctrl_priv),
+	.ops		= &starfive_pinctrl_ops,
+	.probe		= jh7110_aon_pinctrl_probe,
+};
+
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
new file mode 100755
index 0000000000..4e761641eb
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_SYS_NGPIO		64
+#define JH7110_SYS_GC_BASE		0
+
+/* registers */
+#define JH7110_SYS_DOEN			0x000
+#define JH7110_SYS_DOUT			0x040
+#define JH7110_SYS_GPI			0x080
+#define JH7110_SYS_GPIOIN		0x118
+
+#define JH7110_SYS_GPIOEN		0x0dc
+#define JH7110_SYS_GPIOIS0		0x0e0
+#define JH7110_SYS_GPIOIS1		0x0e4
+#define JH7110_SYS_GPIOIC0		0x0e8
+#define JH7110_SYS_GPIOIC1		0x0ec
+#define JH7110_SYS_GPIOIBE0		0x0f0
+#define JH7110_SYS_GPIOIBE1		0x0f4
+#define JH7110_SYS_GPIOIEV0		0x0f8
+#define JH7110_SYS_GPIOIEV1		0x0fc
+#define JH7110_SYS_GPIOIE0		0x100
+#define JH7110_SYS_GPIOIE1		0x104
+#define JH7110_SYS_GPIORIS0		0x108
+#define JH7110_SYS_GPIORIS1		0x10c
+#define JH7110_SYS_GPIOMIS0		0x110
+#define JH7110_SYS_GPIOMIS1		0x114
+
+#define SYS_GPO_PDA_0_74_CFG		0x120
+#define SYS_GPO_PDA_89_94_CFG		0x284
+
+static const struct starfive_pinctrl_pin jh7110_sys_pins[] = {
+	STARFIVE_PINCTRL(PAD_GPIO0,		"GPIO0"),
+	STARFIVE_PINCTRL(PAD_GPIO1,		"GPIO1"),
+	STARFIVE_PINCTRL(PAD_GPIO2,		"GPIO2"),
+	STARFIVE_PINCTRL(PAD_GPIO3,		"GPIO3"),
+	STARFIVE_PINCTRL(PAD_GPIO4,		"GPIO4"),
+	STARFIVE_PINCTRL(PAD_GPIO5,		"GPIO5"),
+	STARFIVE_PINCTRL(PAD_GPIO6,		"GPIO6"),
+	STARFIVE_PINCTRL(PAD_GPIO7,		"GPIO7"),
+	STARFIVE_PINCTRL(PAD_GPIO8,		"GPIO8"),
+	STARFIVE_PINCTRL(PAD_GPIO9,		"GPIO9"),
+	STARFIVE_PINCTRL(PAD_GPIO10,		"GPIO10"),
+	STARFIVE_PINCTRL(PAD_GPIO11,		"GPIO11"),
+	STARFIVE_PINCTRL(PAD_GPIO12,		"GPIO12"),
+	STARFIVE_PINCTRL(PAD_GPIO13,		"GPIO13"),
+	STARFIVE_PINCTRL(PAD_GPIO14,		"GPIO14"),
+	STARFIVE_PINCTRL(PAD_GPIO15,		"GPIO15"),
+	STARFIVE_PINCTRL(PAD_GPIO16,		"GPIO16"),
+	STARFIVE_PINCTRL(PAD_GPIO17,		"GPIO17"),
+	STARFIVE_PINCTRL(PAD_GPIO18,		"GPIO18"),
+	STARFIVE_PINCTRL(PAD_GPIO19,		"GPIO19"),
+	STARFIVE_PINCTRL(PAD_GPIO20,		"GPIO20"),
+	STARFIVE_PINCTRL(PAD_GPIO21,		"GPIO21"),
+	STARFIVE_PINCTRL(PAD_GPIO22,		"GPIO22"),
+	STARFIVE_PINCTRL(PAD_GPIO23,		"GPIO23"),
+	STARFIVE_PINCTRL(PAD_GPIO24,		"GPIO24"),
+	STARFIVE_PINCTRL(PAD_GPIO25,		"GPIO25"),
+	STARFIVE_PINCTRL(PAD_GPIO26,		"GPIO26"),
+	STARFIVE_PINCTRL(PAD_GPIO27,		"GPIO27"),
+	STARFIVE_PINCTRL(PAD_GPIO28,		"GPIO28"),
+	STARFIVE_PINCTRL(PAD_GPIO29,		"GPIO29"),
+	STARFIVE_PINCTRL(PAD_GPIO30,		"GPIO30"),
+	STARFIVE_PINCTRL(PAD_GPIO31,		"GPIO31"),
+	STARFIVE_PINCTRL(PAD_GPIO32,		"GPIO32"),
+	STARFIVE_PINCTRL(PAD_GPIO33,		"GPIO33"),
+	STARFIVE_PINCTRL(PAD_GPIO34,		"GPIO34"),
+	STARFIVE_PINCTRL(PAD_GPIO35,		"GPIO35"),
+	STARFIVE_PINCTRL(PAD_GPIO36,		"GPIO36"),
+	STARFIVE_PINCTRL(PAD_GPIO37,		"GPIO37"),
+	STARFIVE_PINCTRL(PAD_GPIO38,		"GPIO38"),
+	STARFIVE_PINCTRL(PAD_GPIO39,		"GPIO39"),
+	STARFIVE_PINCTRL(PAD_GPIO40,		"GPIO40"),
+	STARFIVE_PINCTRL(PAD_GPIO41,		"GPIO41"),
+	STARFIVE_PINCTRL(PAD_GPIO42,		"GPIO42"),
+	STARFIVE_PINCTRL(PAD_GPIO43,		"GPIO43"),
+	STARFIVE_PINCTRL(PAD_GPIO44,		"GPIO44"),
+	STARFIVE_PINCTRL(PAD_GPIO45,		"GPIO45"),
+	STARFIVE_PINCTRL(PAD_GPIO46,		"GPIO46"),
+	STARFIVE_PINCTRL(PAD_GPIO47,		"GPIO47"),
+	STARFIVE_PINCTRL(PAD_GPIO48,		"GPIO48"),
+	STARFIVE_PINCTRL(PAD_GPIO49,		"GPIO49"),
+	STARFIVE_PINCTRL(PAD_GPIO50,		"GPIO50"),
+	STARFIVE_PINCTRL(PAD_GPIO51,		"GPIO51"),
+	STARFIVE_PINCTRL(PAD_GPIO52,		"GPIO52"),
+	STARFIVE_PINCTRL(PAD_GPIO53,		"GPIO53"),
+	STARFIVE_PINCTRL(PAD_GPIO54,		"GPIO54"),
+	STARFIVE_PINCTRL(PAD_GPIO55,		"GPIO55"),
+	STARFIVE_PINCTRL(PAD_GPIO56,		"GPIO56"),
+	STARFIVE_PINCTRL(PAD_GPIO57,		"GPIO57"),
+	STARFIVE_PINCTRL(PAD_GPIO58,		"GPIO58"),
+	STARFIVE_PINCTRL(PAD_GPIO59,		"GPIO59"),
+	STARFIVE_PINCTRL(PAD_GPIO60,		"GPIO60"),
+	STARFIVE_PINCTRL(PAD_GPIO61,		"GPIO61"),
+	STARFIVE_PINCTRL(PAD_GPIO62,		"GPIO62"),
+	STARFIVE_PINCTRL(PAD_GPIO63,		"GPIO63"),
+	STARFIVE_PINCTRL(PAD_SD0_CLK,		"SD0_CLK"),
+	STARFIVE_PINCTRL(PAD_SD0_CMD,		"SD0_CMD"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA0,		"SD0_DATA0"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA1,		"SD0_DATA1"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA2,		"SD0_DATA2"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA3,		"SD0_DATA3"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA4,		"SD0_DATA4"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA5,		"SD0_DATA5"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA6,		"SD0_DATA6"),
+	STARFIVE_PINCTRL(PAD_SD0_DATA7,		"SD0_DATA7"),
+	STARFIVE_PINCTRL(PAD_SD0_STRB,		"SD0_STRB"),
+	STARFIVE_PINCTRL(PAD_GMAC1_MDC,		"GMAC1_MDC"),
+	STARFIVE_PINCTRL(PAD_GMAC1_MDIO,	"GMAC1_MDIO"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXD0,	"GMAC1_RXD0"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXD1,	"GMAC1_RXD1"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXD2,	"GMAC1_RXD2"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXD3,	"GMAC1_RXD3"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXDV,	"GMAC1_RXDV"),
+	STARFIVE_PINCTRL(PAD_GMAC1_RXC,		"GMAC1_RXC"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXD0,	"GMAC1_TXD0"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXD1,	"GMAC1_TXD1"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXD2,	"GMAC1_TXD2"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXD3,	"GMAC1_TXD3"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXEN,	"GMAC1_TXEN"),
+	STARFIVE_PINCTRL(PAD_GMAC1_TXC,		"GMAC1_TXC"),
+	STARFIVE_PINCTRL(PAD_QSPI_SCLK,		"QSPI_SCLK"),
+	STARFIVE_PINCTRL(PAD_QSPI_CS0,		"QSPI_CS0"),
+	STARFIVE_PINCTRL(PAD_QSPI_DATA0,	"QSPI_DATA0"),
+	STARFIVE_PINCTRL(PAD_QSPI_DATA1,	"QSPI_DATA1"),
+	STARFIVE_PINCTRL(PAD_QSPI_DATA2,	"QSPI_DATA2"),
+	STARFIVE_PINCTRL(PAD_QSPI_DATA3,	"QSPI_DATA3"),
+};
+
+struct jh7110_func_sel {
+	u16 offset;
+	u8 shift;
+	u8 max;
+};
+
+static const struct jh7110_func_sel
+	jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+	[PAD_GMAC1_RXC] = { 0x29c,  0, 1 },
+	[PAD_GPIO10]    = { 0x29c,  2, 3 },
+	[PAD_GPIO11]    = { 0x29c,  5, 3 },
+	[PAD_GPIO12]    = { 0x29c,  8, 3 },
+	[PAD_GPIO13]    = { 0x29c, 11, 3 },
+	[PAD_GPIO14]    = { 0x29c, 14, 3 },
+	[PAD_GPIO15]    = { 0x29c, 17, 3 },
+	[PAD_GPIO16]    = { 0x29c, 20, 3 },
+	[PAD_GPIO17]    = { 0x29c, 23, 3 },
+	[PAD_GPIO18]    = { 0x29c, 26, 3 },
+	[PAD_GPIO19]    = { 0x29c, 29, 3 },
+
+	[PAD_GPIO20]    = { 0x2a0,  0, 3 },
+	[PAD_GPIO21]    = { 0x2a0,  3, 3 },
+	[PAD_GPIO22]    = { 0x2a0,  6, 3 },
+	[PAD_GPIO23]    = { 0x2a0,  9, 3 },
+	[PAD_GPIO24]    = { 0x2a0, 12, 3 },
+	[PAD_GPIO25]    = { 0x2a0, 15, 3 },
+	[PAD_GPIO26]    = { 0x2a0, 18, 3 },
+	[PAD_GPIO27]    = { 0x2a0, 21, 3 },
+	[PAD_GPIO28]    = { 0x2a0, 24, 3 },
+	[PAD_GPIO29]    = { 0x2a0, 27, 3 },
+
+	[PAD_GPIO30]    = { 0x2a4,  0, 3 },
+	[PAD_GPIO31]    = { 0x2a4,  3, 3 },
+	[PAD_GPIO32]    = { 0x2a4,  6, 3 },
+	[PAD_GPIO33]    = { 0x2a4,  9, 3 },
+	[PAD_GPIO34]    = { 0x2a4, 12, 3 },
+	[PAD_GPIO35]    = { 0x2a4, 15, 3 },
+	[PAD_GPIO36]    = { 0x2a4, 17, 3 },
+	[PAD_GPIO37]    = { 0x2a4, 20, 3 },
+	[PAD_GPIO38]    = { 0x2a4, 23, 3 },
+	[PAD_GPIO39]    = { 0x2a4, 26, 3 },
+	[PAD_GPIO40]    = { 0x2a4, 29, 3 },
+
+	[PAD_GPIO41]    = { 0x2a8,  0, 3 },
+	[PAD_GPIO42]    = { 0x2a8,  3, 3 },
+	[PAD_GPIO43]    = { 0x2a8,  6, 3 },
+	[PAD_GPIO44]    = { 0x2a8,  9, 3 },
+	[PAD_GPIO45]    = { 0x2a8, 12, 3 },
+	[PAD_GPIO46]    = { 0x2a8, 15, 3 },
+	[PAD_GPIO47]    = { 0x2a8, 18, 3 },
+	[PAD_GPIO48]    = { 0x2a8, 21, 3 },
+	[PAD_GPIO49]    = { 0x2a8, 24, 3 },
+	[PAD_GPIO50]    = { 0x2a8, 27, 3 },
+	[PAD_GPIO51]    = { 0x2a8, 30, 3 },
+
+	[PAD_GPIO52]    = { 0x2ac,  0, 3 },
+	[PAD_GPIO53]    = { 0x2ac,  2, 3 },
+	[PAD_GPIO54]    = { 0x2ac,  4, 3 },
+	[PAD_GPIO55]    = { 0x2ac,  6, 3 },
+	[PAD_GPIO56]    = { 0x2ac,  9, 3 },
+	[PAD_GPIO57]    = { 0x2ac, 12, 3 },
+	[PAD_GPIO58]    = { 0x2ac, 15, 3 },
+	[PAD_GPIO59]    = { 0x2ac, 18, 3 },
+	[PAD_GPIO60]    = { 0x2ac, 21, 3 },
+	[PAD_GPIO61]    = { 0x2ac, 24, 3 },
+	[PAD_GPIO62]    = { 0x2ac, 27, 3 },
+	[PAD_GPIO63]    = { 0x2ac, 30, 3 },
+
+	[PAD_GPIO6]     = { 0x2b0,  0, 3 },
+	[PAD_GPIO7]     = { 0x2b0,  2, 3 },
+	[PAD_GPIO8]     = { 0x2b0,  5, 3 },
+	[PAD_GPIO9]     = { 0x2b0,  8, 3 },
+};
+
+struct jh7110_vin_group_sel {
+	u16 offset;
+	u8 shift;
+	u8 group;
+};
+
+static const struct jh7110_vin_group_sel
+	jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+	[PAD_GPIO6]     = { 0x2b4, 21, 0 },
+	[PAD_GPIO7]     = { 0x2b4, 18, 0 },
+	[PAD_GPIO8]     = { 0x2b4, 15, 0 },
+	[PAD_GPIO9]     = { 0x2b0, 11, 0 },
+	[PAD_GPIO10]    = { 0x2b0, 20, 0 },
+	[PAD_GPIO11]    = { 0x2b0, 23, 0 },
+	[PAD_GPIO12]    = { 0x2b0, 26, 0 },
+	[PAD_GPIO13]    = { 0x2b0, 29, 0 },
+	[PAD_GPIO14]    = { 0x2b4,  0, 0 },
+	[PAD_GPIO15]    = { 0x2b4,  3, 0 },
+	[PAD_GPIO16]    = { 0x2b4,  6, 0 },
+	[PAD_GPIO17]    = { 0x2b4,  9, 0 },
+	[PAD_GPIO18]    = { 0x2b4, 12, 0 },
+	[PAD_GPIO19]    = { 0x2b0, 14, 0 },
+	[PAD_GPIO20]    = { 0x2b0, 17, 0 },
+
+	[PAD_GPIO21]    = { 0x2b4, 21, 1 },
+	[PAD_GPIO22]    = { 0x2b4, 18, 1 },
+	[PAD_GPIO23]    = { 0x2b4, 15, 1 },
+	[PAD_GPIO24]    = { 0x2b0, 11, 1 },
+	[PAD_GPIO25]    = { 0x2b0, 20, 1 },
+	[PAD_GPIO26]    = { 0x2b0, 23, 1 },
+	[PAD_GPIO27]    = { 0x2b0, 26, 1 },
+	[PAD_GPIO28]    = { 0x2b0, 29, 1 },
+	[PAD_GPIO29]    = { 0x2b4,  0, 1 },
+	[PAD_GPIO30]    = { 0x2b4,  3, 1 },
+	[PAD_GPIO31]    = { 0x2b4,  6, 1 },
+	[PAD_GPIO32]    = { 0x2b4,  9, 1 },
+	[PAD_GPIO33]    = { 0x2b4, 12, 1 },
+	[PAD_GPIO34]    = { 0x2b0, 14, 1 },
+	[PAD_GPIO35]    = { 0x2b0, 17, 1 },
+
+	[PAD_GPIO36]    = { 0x2b4, 21, 2 },
+	[PAD_GPIO37]    = { 0x2b4, 18, 2 },
+	[PAD_GPIO38]    = { 0x2b4, 15, 2 },
+	[PAD_GPIO39]    = { 0x2b0, 11, 2 },
+	[PAD_GPIO40]    = { 0x2b0, 20, 2 },
+	[PAD_GPIO41]    = { 0x2b0, 23, 2 },
+	[PAD_GPIO42]    = { 0x2b0, 26, 2 },
+	[PAD_GPIO43]    = { 0x2b0, 29, 2 },
+	[PAD_GPIO44]    = { 0x2b4,  0, 2 },
+	[PAD_GPIO45]    = { 0x2b4,  3, 2 },
+	[PAD_GPIO46]    = { 0x2b4,  6, 2 },
+	[PAD_GPIO47]    = { 0x2b4,  9, 2 },
+	[PAD_GPIO48]    = { 0x2b4, 12, 2 },
+	[PAD_GPIO49]    = { 0x2b0, 14, 2 },
+	[PAD_GPIO50]    = { 0x2b0, 17, 2 },
+};
+
+static void jh7110_set_function(struct udevice *dev,
+		unsigned int pin, u32 func)
+{
+	const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	void __iomem *reg;
+	u32 mask;
+
+	if (!fs->offset)
+		return;
+
+	if (func > fs->max)
+		return;
+
+	reg = priv->base + fs->offset;
+	func = func << fs->shift;
+	mask = 0x3U << fs->shift;
+
+	func |= readl(reg) & ~mask;
+	writel(func, reg);
+}
+
+static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin)
+{
+	const struct jh7110_vin_group_sel *gs =
+		&jh7110_sys_vin_group_sel[pin];
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	void __iomem *reg;
+	u32 mask;
+	u32 grp;
+
+	if (!gs->offset)
+		return;
+
+	reg = priv->base + gs->offset;
+	grp = gs->group << gs->shift;
+	mask = 0x3U << gs->shift;
+
+	grp |= readl(reg) & ~mask;
+	writel(grp, reg);
+}
+
+static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+		unsigned int din, u32 dout, u32 doen, u32 func)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+	if (pin < priv->info->ngpios && func == 0)
+		starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+	jh7110_set_function(dev, pin, func);
+
+	if (pin < priv->info->ngpios && func == 2)
+		jh7110_set_vin_group(dev, pin);
+
+	return 0;
+}
+
+static int jh7110_sys_get_padcfg_base(struct udevice *dev,
+		unsigned int pin)
+{
+	if (pin < PAD_GMAC1_MDC)
+		return SYS_GPO_PDA_0_74_CFG;
+	else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
+		return SYS_GPO_PDA_89_94_CFG;
+	else
+		return -1;
+}
+
+static void jh7110_sys_init_hw(struct udevice *dev)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+	/* mask all GPIO interrupts */
+	writel(0U, priv->base + JH7110_SYS_GPIOIE0);
+	writel(0U, priv->base + JH7110_SYS_GPIOIE1);
+	/* clear edge interrupt flags */
+	writel(~0U, priv->base + JH7110_SYS_GPIOIC0);
+	writel(~0U, priv->base + JH7110_SYS_GPIOIC1);
+	/* enable GPIO interrupts */
+	writel(1U, priv->base + JH7110_SYS_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
+	/* pin conf */
+	.set_one_pinmux = jh7110_sys_set_one_pin_mux,
+	.get_padcfg_base = jh7110_sys_get_padcfg_base,
+
+	/* gpio dout/doen/din/gpioinput register */
+	.dout_reg_base = JH7110_SYS_DOUT,
+	.dout_mask = GENMASK(6, 0),
+	.doen_reg_base = JH7110_SYS_DOEN,
+	.doen_mask = GENMASK(5, 0),
+	.gpi_reg_base = JH7110_SYS_GPI,
+	.gpi_mask = GENMASK(6, 0),
+	.gpioin_reg_base = JH7110_SYS_GPIOIN,
+
+	/* gpio */
+	.gpio_bank_name = "GPIO",
+	.ngpios = JH7110_SYS_NGPIO,
+	.gpio_init_hw = jh7110_sys_init_hw,
+};
+
+static int jh7110_sys_pinctrl_probe(struct udevice *dev)
+{
+	struct starfive_pinctrl_soc_info *info =
+		(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+	return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
+	/* JH7110 sys pinctrl */
+	{ .compatible = "starfive,jh7110-sys-pinctrl",
+	  .data = (ulong)&jh7110_sys_pinctrl_info, },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_sys_pinctrl) = {
+	.name		= "jh7110-sys-pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= jh7110_sys_pinctrl_ids,
+	.priv_auto	= sizeof(struct starfive_pinctrl_priv),
+	.ops		= &starfive_pinctrl_ops,
+	.probe		= jh7110_sys_pinctrl_probe,
+};
+
+
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
new file mode 100755
index 0000000000..6e69654550
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7100 SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm/device_compat.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+/* pad control bits */
+#define STARFIVE_PADCFG_POS	BIT(7)
+#define STARFIVE_PADCFG_SMT	BIT(6)
+#define STARFIVE_PADCFG_SLEW	BIT(5)
+#define STARFIVE_PADCFG_PD	BIT(4)
+#define STARFIVE_PADCFG_PU	BIT(3)
+#define STARFIVE_PADCFG_BIAS	(STARFIVE_PADCFG_PD | STARFIVE_PADCFG_PU)
+#define STARFIVE_PADCFG_DS_MASK	GENMASK(2, 1)
+#define STARFIVE_PADCFG_DS_2MA	(0U << 1)
+#define STARFIVE_PADCFG_DS_4MA	(1U << 1)
+#define STARFIVE_PADCFG_DS_8MA	(2U << 1)
+#define STARFIVE_PADCFG_DS_12MA	(3U << 1)
+#define STARFIVE_PADCFG_IE	BIT(0)
+#define GPIO_NUM_PER_WORD	32
+
+/*
+ * The packed pinmux values from the device tree look like this:
+ *
+ *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   | 7 - 0 |
+ *  |   din   |  dout   |  doen   | function |  pin  |
+ */
+static unsigned int starfive_pinmux_din(u32 v)
+{
+	return (v & GENMASK(31, 24)) >> 24;
+}
+
+static u32 starfive_pinmux_dout(u32 v)
+{
+	return (v & GENMASK(23, 16)) >> 16;
+}
+
+static u32 starfive_pinmux_doen(u32 v)
+{
+	return (v & GENMASK(15, 10)) >> 10;
+}
+
+static u32 starfive_pinmux_function(u32 v)
+{
+	return (v & GENMASK(9, 8)) >> 8;
+}
+
+static unsigned int starfive_pinmux_pin(u32 v)
+{
+	return v & GENMASK(7, 0);
+}
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+		unsigned int din, u32 dout, u32 doen)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct starfive_pinctrl_soc_info *info = priv->info;
+
+	unsigned int offset = 4 * (pin / 4);
+	unsigned int shift  = 8 * (pin % 4);
+	u32 dout_mask = info->dout_mask << shift;
+	u32 done_mask = info->doen_mask << shift;
+	u32 ival, imask;
+	void __iomem *reg_dout;
+	void __iomem *reg_doen;
+	void __iomem *reg_din;
+
+	reg_dout = priv->base + info->dout_reg_base + offset;
+	reg_doen = priv->base + info->doen_reg_base + offset;
+	dout <<= shift;
+	doen <<= shift;
+	if (din != GPI_NONE) {
+		unsigned int ioffset = 4 * (din / 4);
+		unsigned int ishift  = 8 * (din % 4);
+
+		reg_din = priv->base + info->gpi_reg_base + ioffset;
+		ival = (pin + 2) << ishift;
+		imask = info->gpi_mask << ishift;
+	} else {
+		reg_din = NULL;
+	}
+
+	dout |= readl(reg_dout) & ~dout_mask;
+	writel(dout, reg_dout);
+	doen |= readl(reg_doen) & ~done_mask;
+	writel(doen, reg_doen);
+	if (reg_din) {
+		ival |= readl(reg_din) & ~imask;
+		writel(ival, reg_din);
+	}
+}
+
+static int starfive_pinctrl_set_state_subnode(struct udevice *dev,
+		ofnode node)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+	int ret, i;
+	int npins;
+	u32 *pinmux;
+
+	npins = ofnode_read_size(node, "pinmux") / sizeof(u32);
+	if (npins < 1)
+		return -EINVAL;
+
+	pinmux = kcalloc(npins, sizeof(*pinmux), GFP_KERNEL);
+	if (!pinmux)
+		return -ENOMEM;
+
+	ret = ofnode_read_u32_array(node, "pinmux", pinmux, npins);
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < npins; i++) {
+		u32 v = pinmux[i];
+
+		if (info->set_one_pinmux)
+			info->set_one_pinmux(dev,
+				starfive_pinmux_pin(v),
+				starfive_pinmux_din(v),
+				starfive_pinmux_dout(v),
+				starfive_pinmux_doen(v),
+				starfive_pinmux_function(v));
+	}
+
+	return 0;
+}
+
+/*
+ * starfive_pinctrl_set_state: configure a pin state.
+ * @dev: pin controller device
+ * @config: pseudo device pointing to config node
+ */
+int starfive_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	ofnode node;
+	int ret;
+
+	dev_for_each_subnode(node, config) {
+		ret = starfive_pinctrl_set_state_subnode(dev, node);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct pinconf_param starfive_pinconf_params[] = {
+	{ "bias-disable",	PIN_CONFIG_BIAS_DISABLE,	0 },
+	{ "bias-pull-up",	PIN_CONFIG_BIAS_PULL_UP,	1 },
+	{ "bias-pull-down",	PIN_CONFIG_BIAS_PULL_DOWN,	1 },
+	{ "drive-strength",	PIN_CONFIG_DRIVE_STRENGTH,	0 },
+	{ "input-schmitt-enable",  PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
+	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
+	{ "input-enable",	PIN_CONFIG_INPUT_ENABLE,	1 },
+	{ "input-disable",	PIN_CONFIG_INPUT_ENABLE,	0 },
+	{ "slew-rate",		PIN_CONFIG_SLEW_RATE,		0 },
+};
+
+static const u8 starfive_drive_strength_mA[4] = { 2, 4, 8, 12 };
+
+static u32 starfive_padcfg_ds_from_mA(u32 v)
+{
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		if (v <= starfive_drive_strength_mA[i])
+			break;
+	}
+	return i << 1;
+}
+
+static void starfive_padcfg_rmw(struct udevice *dev,
+		unsigned int pin, u32 mask, u32 value)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+	void __iomem *reg;
+	int padcfg_base;
+
+	if (!info->get_padcfg_base)
+		return;
+
+	padcfg_base = info->get_padcfg_base(dev, pin);
+	if (padcfg_base < 0)
+		return;
+
+	reg = priv->base + padcfg_base + 4 * pin;
+	value &= mask;
+
+	value |= readl(reg) & ~mask;
+	writel(value, reg);
+}
+
+static int starfive_pinconf_set(struct udevice *dev, unsigned int pin,
+		unsigned int param, unsigned int arg)
+{
+	u16 mask = 0;
+	u16 value = 0;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+		mask |= STARFIVE_PADCFG_BIAS;
+		value &= ~STARFIVE_PADCFG_BIAS;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		if (arg == 0)
+			return -ENOTSUPP;
+		mask |= STARFIVE_PADCFG_BIAS;
+		value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PD;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		if (arg == 0)
+			return -ENOTSUPP;
+		mask |= STARFIVE_PADCFG_BIAS;
+		value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PU;
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		mask |= STARFIVE_PADCFG_DS_MASK;
+		value = (value & ~STARFIVE_PADCFG_DS_MASK) |
+			starfive_padcfg_ds_from_mA(arg);
+		break;
+	case PIN_CONFIG_INPUT_ENABLE:
+		mask |= STARFIVE_PADCFG_IE;
+		if (arg)
+			value |= STARFIVE_PADCFG_IE;
+		else
+			value &= ~STARFIVE_PADCFG_IE;
+		break;
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		mask |= STARFIVE_PADCFG_SMT;
+		if (arg)
+			value |= STARFIVE_PADCFG_SMT;
+		else
+			value &= ~STARFIVE_PADCFG_SMT;
+		break;
+	case PIN_CONFIG_SLEW_RATE:
+		mask |= STARFIVE_PADCFG_SLEW;
+		if (arg)
+			value |= STARFIVE_PADCFG_SLEW;
+		else
+			value &= ~STARFIVE_PADCFG_SLEW;
+		break;
+	default:
+		return -ENOTSUPP;
+	}
+
+	starfive_padcfg_rmw(dev, pin, mask, value);
+
+	return 0;
+}
+
+const struct pinctrl_ops starfive_pinctrl_ops = {
+	.set_state = starfive_pinctrl_set_state,
+	.pinconf_num_params	= ARRAY_SIZE(starfive_pinconf_params),
+	.pinconf_params		= starfive_pinconf_params,
+	.pinconf_set		= starfive_pinconf_set,
+};
+
+static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off)
+{
+	struct udevice *pdev = dev->parent;
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+
+	/* enable input and schmitt trigger */
+	starfive_padcfg_rmw(pdev, off,
+			STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT,
+			STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT);
+
+	if (info->set_one_pinmux)
+		info->set_one_pinmux(pdev, off,
+				GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
+
+	return 0;
+}
+
+static int starfive_gpio_direction_output(struct udevice *dev,
+		unsigned int off, int val)
+{
+	struct udevice *pdev = dev->parent;
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+
+	if (info->set_one_pinmux)
+		info->set_one_pinmux(pdev, off,
+				GPI_NONE, val ? GPOUT_HIGH : GPOUT_LOW,
+				GPOEN_ENABLE, 0);
+
+	/* disable input, schmitt trigger and bias */
+	starfive_padcfg_rmw(pdev, off,
+			STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT
+			| STARFIVE_PADCFG_BIAS,
+			0);
+
+	return 0;
+}
+
+static int starfive_gpio_get_value(struct udevice *dev, unsigned int off)
+{
+	struct udevice *pdev = dev->parent;
+	struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+
+	void __iomem *reg = priv->base + info->gpioin_reg_base
+			+ 4 * (off / GPIO_NUM_PER_WORD);
+
+	return !!(readl(reg) & BIT(off % GPIO_NUM_PER_WORD));
+}
+
+static int starfive_gpio_set_value(struct udevice *dev,
+		unsigned int off, int val)
+{
+	struct udevice *pdev = dev->parent;
+	struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+
+	unsigned int offset = 4 * (off / 4);
+	unsigned int shift  = 8 * (off % 4);
+	void __iomem *reg_dout = priv->base + info->dout_reg_base + offset;
+	u32 dout = (val ? GPOUT_HIGH : GPOUT_LOW) << shift;
+	u32 mask = info->dout_mask << shift;
+
+	dout |= readl(reg_dout) & ~mask;
+	writel(dout, reg_dout);
+
+	return 0;
+}
+
+static int starfive_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv;
+	struct udevice *pdev = dev->parent;
+	struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+	struct starfive_pinctrl_soc_info *info = priv->info;
+
+	uc_priv = dev_get_uclass_priv(dev);
+	uc_priv->bank_name = info->gpio_bank_name;
+	uc_priv->gpio_count = info->ngpios;
+
+	if (!info->gpio_init_hw)
+		return -ENXIO;
+
+	info->gpio_init_hw(pdev);
+
+	return 0;
+}
+
+static const struct dm_gpio_ops starfive_gpio_ops = {
+	.direction_input = starfive_gpio_direction_input,
+	.direction_output = starfive_gpio_direction_output,
+	.get_value = starfive_gpio_get_value,
+	.set_value = starfive_gpio_set_value,
+};
+
+static struct driver starfive_gpio_driver = {
+	.name = "starfive_gpio",
+	.id = UCLASS_GPIO,
+	.probe = starfive_gpio_probe,
+	.ops = &starfive_gpio_ops,
+};
+
+static int starfive_gpiochip_register(struct udevice *parent)
+{
+	struct uclass_driver *drv;
+	struct udevice *dev;
+	int ret;
+	ofnode node;
+
+	drv = lists_uclass_lookup(UCLASS_GPIO);
+	if (!drv)
+		return -ENOENT;
+
+	node = dev_ofnode(parent);
+	ret = device_bind_with_driver_data(parent, &starfive_gpio_driver,
+			"starfive_gpio", 0, node, &dev);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int starfive_pinctrl_probe(struct udevice *dev,
+		const struct starfive_pinctrl_soc_info *info)
+{
+	struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* Bind pinctrl_info from .data to priv */
+	priv->info =
+		(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+	if (!priv->info)
+		return -EINVAL;
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	/* gpiochip register */
+	ret = starfive_gpiochip_register(dev);
+	if (ret)
+		return ret;
+
+	dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n",
+			priv->info->ngpios);
+
+	return 0;
+}
+
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h
new file mode 100755
index 0000000000..02b87ca996
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl / GPIO driver for StarFive SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+
+#define STARFIVE_PINCTRL(a, b) { .number = a, .name = b }
+
+extern const struct pinctrl_ops starfive_pinctrl_ops;
+
+struct starfive_pinctrl_pin {
+	unsigned int number;
+	const char *name;
+};
+
+struct starfive_pinctrl_soc_info {
+	/* pinctrl */
+	int (*set_one_pinmux)(struct udevice *dev, unsigned int pin,
+			unsigned int din, u32 dout, u32 doen, u32 func);
+	int (*get_padcfg_base)(struct udevice *dev,
+			unsigned int pin);
+
+	/* gpio dout/doen/din/gpioinput register */
+	unsigned int dout_reg_base;
+	unsigned int dout_mask;
+	unsigned int doen_reg_base;
+	unsigned int doen_mask;
+	unsigned int gpi_reg_base;
+	unsigned int gpi_mask;
+	unsigned int gpioin_reg_base;
+
+	/* gpio */
+	const char *gpio_bank_name;
+	int ngpios;
+	void (*gpio_init_hw)(struct udevice *dev);
+};
+
+/*
+ * struct starfive_pinctrl_priv - private data for Starfive pinctrl driver
+ *
+ * @padctl_base: base address of the pinctrl device
+ * @info: SoC specific data & function
+ */
+struct starfive_pinctrl_priv {
+	void __iomem *base;
+	struct starfive_pinctrl_soc_info *info;
+};
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+		unsigned int din, u32 dout, u32 doen);
+int starfive_pinctrl_probe(struct udevice *dev,
+		const struct starfive_pinctrl_soc_info *info);
+
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
new file mode 100644
index 0000000000..287dd5e9f1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/*
+ * mux bits:
+ *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   |  7 - 0  |
+ *  |  din    |  dout   |  doen   | function | gpio nr |
+ *
+ * dout:     output signal
+ * doen:     output enable signal
+ * din:      optional input signal, 0xff = none
+ * function:
+ * gpio nr:  gpio number, 0 - 63
+ */
+#define GPIOMUX(n, dout, doen, din) ( \
+		(((din)  & 0xff) << 24) | \
+		(((dout) & 0xff) << 16) | \
+		(((doen) & 0x3f) << 10) | \
+		((n) & 0x3f))
+
+#define PINMUX(n, func) ((1 << 10) | ((func & 0x3) << 8) | ((n) & 0xff))
+
+/* sys_iomux pin */
+#define	PAD_GPIO0	 0
+#define	PAD_GPIO1	 1
+#define	PAD_GPIO2	 2
+#define	PAD_GPIO3	 3
+#define	PAD_GPIO4	 4
+#define	PAD_GPIO5	 5
+#define	PAD_GPIO6	 6
+#define	PAD_GPIO7	 7
+#define	PAD_GPIO8	 8
+#define	PAD_GPIO9	 9
+#define	PAD_GPIO10	10
+#define	PAD_GPIO11	11
+#define	PAD_GPIO12	12
+#define	PAD_GPIO13	13
+#define	PAD_GPIO14	14
+#define	PAD_GPIO15	15
+#define	PAD_GPIO16	16
+#define	PAD_GPIO17	17
+#define	PAD_GPIO18	18
+#define	PAD_GPIO19	19
+#define	PAD_GPIO20	20
+#define	PAD_GPIO21	21
+#define	PAD_GPIO22	22
+#define	PAD_GPIO23	23
+#define	PAD_GPIO24	24
+#define	PAD_GPIO25	25
+#define	PAD_GPIO26	26
+#define	PAD_GPIO27	27
+#define	PAD_GPIO28	28
+#define	PAD_GPIO29	29
+#define	PAD_GPIO30	30
+#define	PAD_GPIO31	31
+#define	PAD_GPIO32	32
+#define	PAD_GPIO33	33
+#define	PAD_GPIO34	34
+#define	PAD_GPIO35	35
+#define	PAD_GPIO36	36
+#define	PAD_GPIO37	37
+#define	PAD_GPIO38	38
+#define	PAD_GPIO39	39
+#define	PAD_GPIO40	40
+#define	PAD_GPIO41	41
+#define	PAD_GPIO42	42
+#define	PAD_GPIO43	43
+#define	PAD_GPIO44	44
+#define	PAD_GPIO45	45
+#define	PAD_GPIO46	46
+#define	PAD_GPIO47	47
+#define	PAD_GPIO48	48
+#define	PAD_GPIO49	49
+#define	PAD_GPIO50	50
+#define	PAD_GPIO51	51
+#define	PAD_GPIO52	52
+#define	PAD_GPIO53	53
+#define	PAD_GPIO54	54
+#define	PAD_GPIO55	55
+#define	PAD_GPIO56	56
+#define	PAD_GPIO57	57
+#define	PAD_GPIO58	58
+#define	PAD_GPIO59	59
+#define	PAD_GPIO60	60
+#define	PAD_GPIO61	61
+#define	PAD_GPIO62	62
+#define	PAD_GPIO63	63
+#define	PAD_SD0_CLK	64
+#define	PAD_SD0_CMD	65
+#define	PAD_SD0_DATA0	66
+#define	PAD_SD0_DATA1	67
+#define	PAD_SD0_DATA2	68
+#define	PAD_SD0_DATA3	69
+#define	PAD_SD0_DATA4	70
+#define	PAD_SD0_DATA5	71
+#define	PAD_SD0_DATA6	72
+#define	PAD_SD0_DATA7	73
+#define	PAD_SD0_STRB	74
+#define	PAD_GMAC1_MDC	75
+#define	PAD_GMAC1_MDIO	76
+#define	PAD_GMAC1_RXD0	77
+#define	PAD_GMAC1_RXD1	78
+#define	PAD_GMAC1_RXD2	79
+#define	PAD_GMAC1_RXD3	80
+#define	PAD_GMAC1_RXDV	81
+#define	PAD_GMAC1_RXC	82
+#define	PAD_GMAC1_TXD0	83
+#define	PAD_GMAC1_TXD1	84
+#define	PAD_GMAC1_TXD2	85
+#define	PAD_GMAC1_TXD3	86
+#define	PAD_GMAC1_TXEN	87
+#define	PAD_GMAC1_TXC	88
+#define	PAD_QSPI_SCLK	89
+#define	PAD_QSPI_CS0	90
+#define	PAD_QSPI_DATA0	91
+#define	PAD_QSPI_DATA1	92
+#define	PAD_QSPI_DATA2	93
+#define	PAD_QSPI_DATA3	94
+
+/* aon_iomux pin */
+#define	PAD_TESTEN	0
+#define	PAD_RGPIO0	1
+#define	PAD_RGPIO1	2
+#define	PAD_RGPIO2	3
+#define	PAD_RGPIO3	4
+#define	PAD_RSTN	5
+#define	PAD_GMAC0_MDC	6
+#define	PAD_GMAC0_MDIO	7
+#define	PAD_GMAC0_RXD0	8
+#define	PAD_GMAC0_RXD1	9
+#define	PAD_GMAC0_RXD2	10
+#define	PAD_GMAC0_RXD3	11
+#define	PAD_GMAC0_RXDV	12
+#define	PAD_GMAC0_RXC	13
+#define	PAD_GMAC0_TXD0	14
+#define	PAD_GMAC0_TXD1	15
+#define	PAD_GMAC0_TXD2	16
+#define	PAD_GMAC0_TXD3	17
+#define	PAD_GMAC0_TXEN	18
+#define	PAD_GMAC0_TXC	19
+
+/* sys_iomux dout */
+#define GPOUT_LOW				  0
+#define GPOUT_HIGH				  1
+#define GPOUT_SYS_WAVE511_UART_TX		  2
+#define GPOUT_SYS_CAN0_STBY			  3
+#define GPOUT_SYS_CAN0_TST_NEXT_BIT		  4
+#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT		  5
+#define GPOUT_SYS_CAN0_TXD			  6
+#define GPOUT_SYS_USB_DRIVE_VBUS		  7
+#define GPOUT_SYS_QSPI_CS1			  8
+#define GPOUT_SYS_SPDIF				  9
+#define GPOUT_SYS_HDMI_CEC_SDA			 10
+#define GPOUT_SYS_HDMI_DDC_SCL			 11
+#define GPOUT_SYS_HDMI_DDC_SDA			 12
+#define GPOUT_SYS_WATCHDOG			 13
+#define GPOUT_SYS_I2C0_CLK			 14
+#define GPOUT_SYS_I2C0_DATA			 15
+#define GPOUT_SYS_SDIO0_BACK_END_POWER		 16
+#define GPOUT_SYS_SDIO0_CARD_POWER_EN		 17
+#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN	 18
+#define GPOUT_SYS_SDIO0_RST			 19
+#define GPOUT_SYS_UART0_TX			 20
+#define GPOUT_SYS_HIFI4_JTAG_TDO		 21
+#define GPOUT_SYS_JTAG_TDO			 22
+#define GPOUT_SYS_PDM_MCLK			 23
+#define GPOUT_SYS_PWM_CHANNEL0			 24
+#define GPOUT_SYS_PWM_CHANNEL1			 25
+#define GPOUT_SYS_PWM_CHANNEL2			 26
+#define GPOUT_SYS_PWM_CHANNEL3			 27
+#define GPOUT_SYS_PWMDAC_LEFT			 28
+#define GPOUT_SYS_PWMDAC_RIGHT			 29
+#define GPOUT_SYS_SPI0_CLK			 30
+#define GPOUT_SYS_SPI0_FSS			 31
+#define GPOUT_SYS_SPI0_TXD			 32
+#define GPOUT_SYS_GMAC_PHYCLK			 33
+#define GPOUT_SYS_I2SRX_BCLK			 34
+#define GPOUT_SYS_I2SRX_LRCK			 35
+#define GPOUT_SYS_I2STX0_BCLK			 36
+#define GPOUT_SYS_I2STX0_LRCK			 37
+#define GPOUT_SYS_MCLK				 38
+#define GPOUT_SYS_TDM_CLK			 39
+#define GPOUT_SYS_TDM_SYNC			 40
+#define GPOUT_SYS_TDM_TXD			 41
+#define GPOUT_SYS_TRACE_DATA0			 42
+#define GPOUT_SYS_TRACE_DATA1			 43
+#define GPOUT_SYS_TRACE_DATA2			 44
+#define GPOUT_SYS_TRACE_DATA3			 45
+#define GPOUT_SYS_TRACE_REF			 46
+#define GPOUT_SYS_CAN1_STBY			 47
+#define GPOUT_SYS_CAN1_TST_NEXT_BIT		 48
+#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT		 49
+#define GPOUT_SYS_CAN1_TXD			 50
+#define GPOUT_SYS_I2C1_CLK			 51
+#define GPOUT_SYS_I2C1_DATA			 52
+#define GPOUT_SYS_SDIO1_BACK_END_POWER		 53
+#define GPOUT_SYS_SDIO1_CARD_POWER_EN		 54
+#define GPOUT_SYS_SDIO1_CLK			 55
+#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN	 56
+#define GPOUT_SYS_SDIO1_CMD			 57
+#define GPOUT_SYS_SDIO1_DATA0			 58
+#define GPOUT_SYS_SDIO1_DATA1			 59
+#define GPOUT_SYS_SDIO1_DATA2			 60
+#define GPOUT_SYS_SDIO1_DATA3			 61
+#define GPOUT_SYS_SDIO1_DATA4			 63
+#define GPOUT_SYS_SDIO1_DATA5			 63
+#define GPOUT_SYS_SDIO1_DATA6			 64
+#define GPOUT_SYS_SDIO1_DATA7			 65
+#define GPOUT_SYS_SDIO1_RST			 66
+#define GPOUT_SYS_UART1_RTS			 67
+#define GPOUT_SYS_UART1_TX			 68
+#define GPOUT_SYS_I2STX1_SDO0			 69
+#define GPOUT_SYS_I2STX1_SDO1			 70
+#define GPOUT_SYS_I2STX1_SDO2			 71
+#define GPOUT_SYS_I2STX1_SDO3			 72
+#define GPOUT_SYS_SPI1_CLK			 73
+#define GPOUT_SYS_SPI1_FSS			 74
+#define GPOUT_SYS_SPI1_TXD			 75
+#define GPOUT_SYS_I2C2_CLK			 76
+#define GPOUT_SYS_I2C2_DATA			 77
+#define GPOUT_SYS_UART2_RTS			 78
+#define GPOUT_SYS_UART2_TX			 79
+#define GPOUT_SYS_SPI2_CLK			 80
+#define GPOUT_SYS_SPI2_FSS			 81
+#define GPOUT_SYS_SPI2_TXD			 82
+#define GPOUT_SYS_I2C3_CLK			 83
+#define GPOUT_SYS_I2C3_DATA			 84
+#define GPOUT_SYS_UART3_TX			 85
+#define GPOUT_SYS_SPI3_CLK			 86
+#define GPOUT_SYS_SPI3_FSS			 87
+#define GPOUT_SYS_SPI3_TXD			 88
+#define GPOUT_SYS_I2C4_CLK			 89
+#define GPOUT_SYS_I2C4_DATA			 90
+#define GPOUT_SYS_UART4_RTS			 91
+#define GPOUT_SYS_UART4_TX			 92
+#define GPOUT_SYS_SPI4_CLK			 93
+#define GPOUT_SYS_SPI4_FSS			 94
+#define GPOUT_SYS_SPI4_TXD			 95
+#define GPOUT_SYS_I2C5_CLK			 96
+#define GPOUT_SYS_I2C5_DATA			 97
+#define GPOUT_SYS_UART5_RTS			 98
+#define GPOUT_SYS_UART5_TX			 99
+#define GPOUT_SYS_SPI5_CLK			100
+#define GPOUT_SYS_SPI5_FSS			101
+#define GPOUT_SYS_SPI5_TXD			102
+#define GPOUT_SYS_I2C6_CLK			103
+#define GPOUT_SYS_I2C6_DATA			104
+#define GPOUT_SYS_SPI6_CLK			105
+#define GPOUT_SYS_SPI6_FSS			106
+#define GPOUT_SYS_SPI6_TXD			107
+
+/* aon_iomux dout */
+#define GPOUT_AON_CLK_32K_OUT			2
+#define GPOUT_AON_PTC0_PWM4			3
+#define GPOUT_AON_PTC0_PWM5			4
+#define GPOUT_AON_PTC0_PWM6			5
+#define GPOUT_AON_PTC0_PWM7			6
+#define GPOUT_AON_CLK_GCLK0			7
+#define GPOUT_AON_CLK_GCLK1			8
+#define GPOUT_AON_CLK_GCLK2			9
+
+/* sys_iomux doen */
+#define GPOEN_ENABLE				 0
+#define GPOEN_DISABLE				 1
+#define GPOEN_SYS_HDMI_CEC_SDA			 2
+#define GPOEN_SYS_HDMI_DDC_SCL			 3
+#define GPOEN_SYS_HDMI_DDC_SDA			 4
+#define GPOEN_SYS_I2C0_CLK			 5
+#define GPOEN_SYS_I2C0_DATA			 6
+#define GPOEN_SYS_HIFI4_JTAG_TDO		 7
+#define GPOEN_SYS_JTAG_TDO			 8
+#define GPOEN_SYS_PWM0_CHANNEL0			 9
+#define GPOEN_SYS_PWM0_CHANNEL1			10
+#define GPOEN_SYS_PWM0_CHANNEL2			11
+#define GPOEN_SYS_PWM0_CHANNEL3			12
+#define GPOEN_SYS_SPI0_NSSPCTL			13
+#define GPOEN_SYS_SPI0_NSSP			14
+#define GPOEN_SYS_TDM_SYNC			15
+#define GPOEN_SYS_TDM_TXD			16
+#define GPOEN_SYS_I2C1_CLK			17
+#define GPOEN_SYS_I2C1_DATA			18
+#define GPOEN_SYS_SDIO1_CMD			19
+#define GPOEN_SYS_SDIO1_DATA0			20
+#define GPOEN_SYS_SDIO1_DATA1			21
+#define GPOEN_SYS_SDIO1_DATA2			22
+#define GPOEN_SYS_SDIO1_DATA3			23
+#define GPOEN_SYS_SDIO1_DATA4			24
+#define GPOEN_SYS_SDIO1_DATA5			25
+#define GPOEN_SYS_SDIO1_DATA6			26
+#define GPOEN_SYS_SDIO1_DATA7			27
+#define GPOEN_SYS_SPI1_NSSPCTL			28
+#define GPOEN_SYS_SPI1_NSSP			29
+#define GPOEN_SYS_I2C2_CLK			30
+#define GPOEN_SYS_I2C2_DATA			31
+#define GPOEN_SYS_SPI2_NSSPCTL			32
+#define GPOEN_SYS_SPI2_NSSP			33
+#define GPOEN_SYS_I2C3_CLK			34
+#define GPOEN_SYS_I2C3_DATA			35
+#define GPOEN_SYS_SPI3_NSSPCTL			36
+#define GPOEN_SYS_SPI3_NSSP			37
+#define GPOEN_SYS_I2C4_CLK			38
+#define GPOEN_SYS_I2C4_DATA			39
+#define GPOEN_SYS_SPI4_NSSPCTL			40
+#define GPOEN_SYS_SPI4_NSSP			41
+#define GPOEN_SYS_I2C5_CLK			42
+#define GPOEN_SYS_I2C5_DATA			43
+#define GPOEN_SYS_SPI5_NSSPCTL			44
+#define GPOEN_SYS_SPI5_NSSP			45
+#define GPOEN_SYS_I2C6_CLK			46
+#define GPOEN_SYS_I2C6_DATA			47
+#define GPOEN_SYS_SPI6_NSSPCTL			48
+#define GPOEN_SYS_SPI6_NSSP			49
+
+/* aon_iomux doen */
+#define GPOEN_AON_PTC0_OE_N_4			2
+#define GPOEN_AON_PTC0_OE_N_5			3
+#define GPOEN_AON_PTC0_OE_N_6			4
+#define GPOEN_AON_PTC0_OE_N_7			5
+
+/* sys_iomux gin */
+#define GPI_NONE				255
+
+#define GPI_SYS_WAVE511_UART_RX			 0
+#define GPI_SYS_CAN0_RXD			 1
+#define GPI_SYS_USB_OVERCURRENT			 2
+#define GPI_SYS_SPDIF				 3
+#define GPI_SYS_JTAG_RST			 4
+#define GPI_SYS_HDMI_CEC_SDA			 5
+#define GPI_SYS_HDMI_DDC_SCL			 6
+#define GPI_SYS_HDMI_DDC_SDA			 7
+#define GPI_SYS_HDMI_HPD			 8
+#define GPI_SYS_I2C0_CLK			 9
+#define GPI_SYS_I2C0_DATA			10
+#define GPI_SYS_SDIO0_CD			11
+#define GPI_SYS_SDIO0_INT			12
+#define GPI_SYS_SDIO0_WP			13
+#define GPI_SYS_UART0_RX			14
+#define GPI_SYS_HIFI4_JTAG_TCK			15
+#define GPI_SYS_HIFI4_JTAG_TDI			16
+#define GPI_SYS_HIFI4_JTAG_TMS			17
+#define GPI_SYS_HIFI4_JTAG_RST			18
+#define GPI_SYS_JTAG_TDI			19
+#define GPI_SYS_JTAG_TMS			20
+#define GPI_SYS_PDM_DMIC0			21
+#define GPI_SYS_PDM_DMIC1			22
+#define GPI_SYS_I2SRX_SDIN0			23
+#define GPI_SYS_I2SRX_SDIN1			24
+#define GPI_SYS_I2SRX_SDIN2			25
+#define GPI_SYS_SPI0_CLK			26
+#define GPI_SYS_SPI0_FSS			27
+#define GPI_SYS_SPI0_RXD			28
+#define GPI_SYS_JTAG_TCK			29
+#define GPI_SYS_MCLK_EXT			30
+#define GPI_SYS_I2SRX_BCLK			31
+#define GPI_SYS_I2SRX_LRCK			32
+#define GPI_SYS_I2STX0_BCLK			33
+#define GPI_SYS_I2STX0_LRCK			34
+#define GPI_SYS_TDM_CLK				35
+#define GPI_SYS_TDM_RXD				36
+#define GPI_SYS_TDM_SYNC			37
+#define GPI_SYS_CAN1_RXD			38
+#define GPI_SYS_I2C1_CLK			39
+#define GPI_SYS_I2C1_DATA			40
+#define GPI_SYS_SDIO1_CD			41
+#define GPI_SYS_SDIO1_INT			42
+#define GPI_SYS_SDIO1_WP			43
+#define GPI_SYS_SDIO1_CMD			44
+#define GPI_SYS_SDIO1_DATA0			45
+#define GPI_SYS_SDIO1_DATA1			46
+#define GPI_SYS_SDIO1_DATA2			47
+#define GPI_SYS_SDIO1_DATA3			48
+#define GPI_SYS_SDIO1_DATA4			49
+#define GPI_SYS_SDIO1_DATA5			50
+#define GPI_SYS_SDIO1_DATA6			51
+#define GPI_SYS_SDIO1_DATA7			52
+#define GPI_SYS_SDIO1_STRB			53
+#define GPI_SYS_UART1_CTS			54
+#define GPI_SYS_UART1_RX			55
+#define GPI_SYS_SPI1_CLK			56
+#define GPI_SYS_SPI1_FSS			57
+#define GPI_SYS_SPI1_RXD			58
+#define GPI_SYS_I2C2_CLK			59
+#define GPI_SYS_I2C2_DATA			60
+#define GPI_SYS_UART2_CTS			61
+#define GPI_SYS_UART2_RX			62
+#define GPI_SYS_SPI2_CLK			63
+#define GPI_SYS_SPI2_FSS			64
+#define GPI_SYS_SPI2_RXD			65
+#define GPI_SYS_I2C3_CLK			66
+#define GPI_SYS_I2C3_DATA			67
+#define GPI_SYS_UART3_RX			68
+#define GPI_SYS_SPI3_CLK			69
+#define GPI_SYS_SPI3_FSS			70
+#define GPI_SYS_SPI3_RXD			71
+#define GPI_SYS_I2C4_CLK			72
+#define GPI_SYS_I2C4_DATA			73
+#define GPI_SYS_UART4_CTS			74
+#define GPI_SYS_UART4_RX			75
+#define GPI_SYS_SPI4_CLK			76
+#define GPI_SYS_SPI4_FSS			77
+#define GPI_SYS_SPI4_RXD			78
+#define GPI_SYS_I2C5_CLK			79
+#define GPI_SYS_I2C5_DATA			80
+#define GPI_SYS_UART5_CTS			81
+#define GPI_SYS_UART5_RX			82
+#define GPI_SYS_SPI5_CLK			83
+#define GPI_SYS_SPI5_FSS			84
+#define GPI_SYS_SPI5_RXD			85
+#define GPI_SYS_I2C6_CLK			86
+#define GPI_SYS_I2C6_DATA			87
+#define GPI_SYS_SPI6_CLK			88
+#define GPI_SYS_SPI6_FSS			89
+#define GPI_SYS_SPI6_RXD			90
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0		0
+#define GPI_AON_PMU_GPIO_WAKEUP_1		1
+#define GPI_AON_PMU_GPIO_WAKEUP_2		2
+#define GPI_AON_PMU_GPIO_WAKEUP_3		3
+
+#endif