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<title>starfive-tech/u-boot.git/include/efi_riscv.h, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2023-11-29T02:47:33+00:00</updated>
<entry>
<title>efi_loader: Enable RISCV_EFI_BOOT_PROTOCOL support</title>
<updated>2023-11-29T02:47:33+00:00</updated>
<author>
<name>Sunil V L</name>
<email>sunilvl@ventanamicro.com</email>
</author>
<published>2022-01-28T15:18:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=f1428044084cf04e545cd4f5d67ad68adf3f7873'/>
<id>urn:sha1:f1428044084cf04e545cd4f5d67ad68adf3f7873</id>
<content type='text'>
This adds support for new RISCV_EFI_BOOT_PROTOCOL to
communicate the boot hart ID to bootloader/kernel on RISC-V
UEFI platforms.

The specification of the protocol is hosted at:
https://github.com/riscv-non-isa/riscv-uefi

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
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