starfive-tech/u-boot.git/include/dt-bindings, branch rtthread_AMPStarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP2023-04-23T03:19:47+00:00board: starfive: copyright: Standardize the copyright format2023-04-23T03:19:47+00:00Yanhong Wangyanhong.wang@starfivetech.com2023-04-23T03:19:47+00:00urn:sha1:fe8426ebb03dc13a06758d2c4c0571e19b3c064a
Unify the content format of the copyright section
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
clk:starfive: Add vout clock driver for StarFive JH71102023-01-05T10:04:26+00:00Yanhong Wangyanhong.wang@starfivetech.com2022-11-23T02:43:00+00:00urn:sha1:1b96445bfc9f35f55e8fead28ddfcc36325cc964
Add vout clock driver for StarFive JH7110
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions2022-11-21T03:44:15+00:00Jianlong Huangjianlong.huang@starfivetech.com2022-11-06T03:50:59+00:00urn:sha1:1288948b5409bd39fc90a6ff33b9e965518a7838
Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
clk:jh7110: update apb_bus clk relationship2022-10-18T08:24:37+00:00yanhong.wangyanhong.wang@starfivetech.com2022-08-03T07:59:08+00:00urn:sha1:20f3a9aeb57d6237a1a19ae519e23f06d98f88ef
The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
riscv:dts: update clk&reset properties2022-10-18T08:24:35+00:00yanhong.wangyanhong.wang@starfivetech.com2022-05-07T10:17:53+00:00urn:sha1:becd46e20807c56a071be1eaab897bcaeb178c31
Synchronize the kernel dts file
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
clk:starfive-jh7110: Add clock driver for JH71102022-10-18T08:24:34+00:00yanhong.wangyanhong.wang@starfivetech.com2022-04-11T07:24:56+00:00urn:sha1:e9cef6c8ce31ff51099f23e2d628483cf762d728
Add a clock driver for StarFive JH7110 Soc platform.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Reset:Starfive-jh7110: Add reset driver for JH71102022-10-18T08:24:33+00:00yanhong.wangyanhong.wang@starfivetech.com2022-03-18T10:21:46+00:00urn:sha1:56c86383dc88850ee2e5af197532939b861f573b
Support for reset controller on starfive JH7110 SoCs.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
drivers: clk: Add clock driver for Intel N5X device2021-08-25T04:51:53+00:00Siew Chin Limelly.siew.chin.lim@intel.com2021-08-10T03:26:30+00:00urn:sha1:05e1e3befa380c1f4114bfbd877b0b8ca334a5e9
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
rockchip: rk3188-power: sync power domain dt-binding header from Linux2021-08-11T09:54:37+00:00Johan Jonkerjbx6244@gmail.com2021-06-25T13:26:31+00:00urn:sha1:76dccdca2e7e45106b0f1b5498c05056e92c1077
In order to update the DT for rk3188
sync the power domain dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: rk3188-cru-common: sync clock dt-binding header from Linux2021-08-11T09:54:37+00:00Johan Jonkerjbx6244@gmail.com2021-06-25T13:26:29+00:00urn:sha1:571f679d1aa7eb98dcae7691dd34596beda1dfb2
In order to update the DT for rk3066 and rk3188
sync the clock dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>