starfive-tech/u-boot.git/examples/standalone/stubs.c, branch rtthread_AMP

command: Remove the cmd_tbl_t typedef

2020-05-18T22:36:55+00:00

We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass

riscv: support standalone applications on RV64I systems

2019-01-15T01:36:31+00:00

Add an implementation of EXPORT_FUNC() for RV64I systems to support them in standalone applications. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng

riscv: replace use of callee-saved register in standalone

2019-01-15T01:36:31+00:00

Register x19 (s3) is a callee-saved register. It must not be used to load and jump to exported functions without saving it beforehand. Replace it with t0, a temporary and caller-saved register. Change the code comment to reflect this and fix it to correctly list gp as the register with the pointer to global data. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng

riscv: Support standalone

2018-01-12T13:05:12+00:00

Run hello_world successfully. U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) DRAM: 1 GiB MMC: mmc@f0e00000: 0 SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB In: serial@f0300000 Out: serial@f0300000 Err: serial@f0300000 Net: Warning: mac@e0100000 (eth0) using random MAC address - 0a:47:9b:f8:b4:f2 eth0: mac@e0100000 RISC-V # mmc rescan RISC-V # fatls mmc 0:1 318907 u-boot-ae250-64.bin 1252 hello_world_ae250_32.bin 328787 u-boot-ae250-32.bin 3 file(s), 0 dir(s) RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin reading hello_world_ae250_32.bin 1252 bytes read in 23 ms (52.7 KiB/s) RISC-V # go 0x600000 Example expects ABI version 9 Actual U-Boot ABI version 9 Hello World argc = 1 argv[0] = "0x600000" argv[1] = "$B@" Hit any key to exit ... RISC-V # Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu

avr32: Retire AVR32 for good

2017-07-06T20:17:19+00:00

AVR32 is gone. It's already more than two years for no support in Buildroot, even longer there is no support in GCC (last version is heavily patched 4.2.4). Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully). There is no good point to keep this support in U-Boot either. Reviewed-by: Simon Glass Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Signed-off-by: Andy Shevchenko

OpenRISC: Remove

2017-04-05T17:52:34+00:00

The OpenRISC architecture is currently unmaintained, remove. Cc: Stefan Kristiansson Signed-off-by: Tom Rini Reviewed-by: Simon Glass

SPARC: Remove

2017-04-05T17:52:20+00:00

The SPARC architecture is currently unmaintained, remove. Cc: Francois Retief Signed-off-by: Tom Rini

Blackfin: Remove

2017-04-05T17:52:01+00:00

The architecture is currently unmaintained, remove. Cc: Benjamin Matthews Cc: Chong Huang Cc: Dimitar Penev Cc: Haitao Zhang Cc: I-SYST Micromodule Cc: M.Hasewinkel (MHA) Cc: Marek Vasut Cc: Martin Strubel Cc: Peter Meerwald Cc: Sonic Zhang Cc: Valentin Yakovenkov Cc: Wojtek Skulski Cc: Wojtek Skulski Signed-off-by: Tom Rini

xtensa: add support for the xtensa processor architecture [1/2]

2016-08-15T22:46:38+00:00

The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: Chris Zankel Signed-off-by: Max Filippov Reviewed-by: Simon Glass Reviewed-by: Tom Rini

Add support for 64-bit MIPS to examples/standalone

2016-05-20T23:25:50+00:00

Signed-off-by: Stanislav Galabov