starfive-tech/u-boot.git/drivers/watchdog, branch rtthread_AMP

wdt: dw: Fix passing NULL pointer to reset functions

2021-09-20T05:39:29+00:00

reset_*_bulk expects a real pointer. Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function") Signed-off-by: Sean Anderson Reviewed-by: Stefan Roese

watchdog: versal: Include header file needed for dev_ functions

2021-08-26T06:08:11+00:00

dev_dbg, dev_err and dev_warn seems to be moved to different header file. Include dm/device_compat.h file to compile properly. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek

Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2021-07-17T14:52:21+00:00

i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277

mx7ulp: wdog: Wait for WDOG unlock and reconfiguration to complete

2021-07-17T12:59:56+00:00

According to i.MX7ULP Reference Manual we should wait for WDOG unlock and reconfiguration to complete. Section "59.5.3 Configure Watchdog" provides the following example: DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1); while(WDOG_CS[RCS]==0); //wait until new configuration takes effect EnableInterrupts; //enable global interrupt Update U-Boot WDOG driver to align with i.MX7ULP reference manual. Use 32 bits accessing to CS register. According to RM, the bits in this register only can write once after unlock. So using 8 bits access will cause problem. Reviewed-by: Ye Li Signed-off-by: Breno Lima Signed-off-by: Peng Fan

mx7ulp: Update unlock and refresh sequences in sWDOG driver

2021-07-17T12:59:56+00:00

According to i.MX7ULP Reference Manual the second word write for both UNLOCK and REFRESH operations must occur in maximum 16 bus clock. The current code is using writel() function which has a DMB barrier to order the memory access. The DMB between two words write may introduce some delay in certain circumstance, causing a WDOG timeout due to 16 bus clock window requirement. Replace writel() function by __raw_writel() to achieve a faster memory access and avoid such issue. Reviewed-by: Ye Li Signed-off-by: Breno Lima

drivers: watchdog: wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART

2021-07-16T08:28:35+00:00

There is no separate SPL/TPL config for WATCHDOG_AUTOSTART. So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog working in SPL again. Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting watchdog") Signed-off-by: Teresa Remmet Reviewed-by: Stefan Roese

driver: watchdog: reset watchdog in designware_wdt_stop() function

2021-07-16T08:28:35+00:00

In uboot command line environment, watchdog is not able to be stopped with below commands: SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200 SOCFPGA_STRATIX10 # wdt stop Refer to watchdog driver in linux kernel, it is also need to reset watchdog after disable it so that the disable action takes effect. Signed-off-by: Meng Li Reviewed-by: Stefan Roese Reviewed-by: Sean Anderson

dm: define LOG_CATEGORY for all uclass

2021-07-06T16:38:03+00:00

Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass

watchdog: cadence: Add expire_now method

2021-07-01T07:25:06+00:00

It is working in a way that only minimal timeout is setup to reach expiration just right after it is setup. Please make sure that PMUFW is compiled with ENABLE_EM flag. On U-Boot prompt you can test it like: ZynqMP> wdt dev watchdog@fd4d0000 ZynqMP> wdt list watchdog@fd4d0000 (cdns_wdt) ZynqMP> wdt dev dev: watchdog@fd4d0000 ZynqMP> wdt expire (And reset should happen here) Signed-off-by: Michal Simek

watchdog: use time_after_eq() in watchdog_reset()

2021-04-27T06:28:07+00:00

Some boards don't work with the rate-limiting done in the generic watchdog_reset() provided by wdt-uclass. For example, on powerpc, get_timer() ceases working during bootm since interrupts are disabled before the kernel image gets decompressed, and when the decompression takes longer than the watchdog device allows (or enough of the budget that the kernel doesn't get far enough to assume responsibility for petting the watchdog), the result is a non-booting board. As a somewhat hacky workaround (because DT is supposed to describe hardware), allow specifying hw_margin_ms=0 in device tree to effectively disable the ratelimiting and actually ping the watchdog every time watchdog_reset() is called. For that to work, the "has enough time passed" check just needs to be tweaked a little to allow the now==next_reset case as well. Suggested-by: Christophe Leroy Signed-off-by: Rasmus Villemoes Reviewed-by: Stefan Roese