starfive-tech/u-boot.git/drivers/reset, branch rtthread_AMP

board: starfive: copyright: Standardize the copyright format

2023-04-23T03:19:47+00:00

Unify the content format of the copyright section Signed-off-by: Yanhong Wang

reset:starfive:jh7110: Delete redundant logic

2022-10-18T08:24:37+00:00

In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,one group is active high, and the other group is active low. However, the software does not need to distinguish whether the RESET signal is active high or active low,Write 1 to be assert, and write 0 to deassert. Therefore, the software does not need to add additional logic to distinguish these two sets of signals. Signed-off-by: yanhong.wang

SPL:reset:starfive-jh7110: support reset in SPL

2022-10-18T08:24:37+00:00

Update Kconfig to support reset in SPL for StarFive JH7110 SoC. Signed-off-by: yanhong.wang

reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macro

2022-10-18T08:24:35+00:00

Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang

reset:starfive: Adjust judgment conditions

2022-10-18T08:24:34+00:00

The serial driver will call reset driver, udelay function will be called in reset driver, but the timer is not init,so udelay function call will cases error. Signed-off-by: yanhong.wang

Reset:Starfive-jh7110: Add reset driver for JH7110

2022-10-18T08:24:33+00:00

Support for reset controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang

reset: zynqmp: Add reset controller for ZynqMP SoC

2021-08-06T07:32:03+00:00

Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek

reset: ast2600: Fix missing reference operator

2021-07-24T12:57:53+00:00

Fix missing reference operator '&' to correctly get HW register addresses for writel(). Signed-off-by: Chia-Wei Wang

reset: Avoid a warning in devm_reset_bulk_get_by_node()

2021-07-15T22:42:05+00:00

The devres_alloc() function is intended to avoid the need for freeing memory, although in practice it may not be enabled, thus leading to a true leak. Nevertheless this is intended. Add a comment to explain this. Signed-off-by: Simon Glass Reported-by: Coverity (CID: 312952)

reset: uniphier: Add PCIe reset entry

2021-07-14T20:48:06+00:00

Add reset control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi