<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/drivers/mtd/spi, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
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<updated>2022-10-18T08:24:34+00:00</updated>
<entry>
<title>mtd:spi-nor-ids: Add support for GD25LQ256D</title>
<updated>2022-10-18T08:24:34+00:00</updated>
<author>
<name>yanhong.wang</name>
<email>yanhong.wang@starfivetech.com</email>
</author>
<published>2022-04-15T00:53:36+00:00</published>
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<id>urn:sha1:1cf900b76137950e6d16ecf41dc6cf3ad5d9e481</id>
<content type='text'>
Adds support for GigaDevice's spi nor flash

Signed-off-by: yanhong.wang &lt;yanhong.wang@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0</title>
<updated>2021-09-28T16:03:21+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2021-09-14T18:28:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=b81ce79df091834430dce72f0e4d1451f25fc8f7'/>
<id>urn:sha1:b81ce79df091834430dce72f0e4d1451f25fc8f7</id>
<content type='text'>
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as boot media
operate in bus mode 0, so switch that as the default.

This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx
ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble
with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked
as those might need mode 3.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Cc: Andreas Biessmann &lt;andreas@biessmann.org&gt;
Cc: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Cc: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Valentin Longchamp &lt;valentin.longchamp@hitachi-powergrids.com&gt;
Cc: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi: nor: force mtd name to "nor%d"</title>
<updated>2021-09-28T16:03:20+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-09-22T16:29:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=a4f2d83414557f2ad7b63d537e2c31790d0f184d'/>
<id>urn:sha1:a4f2d83414557f2ad7b63d537e2c31790d0f184d</id>
<content type='text'>
Force the mtd name of spi-nor to "nor" + the driver sequence number:
"nor0", "nor1"... beginning after the existing nor devices.

This patch is coherent with existing "nand" and "spi-nand"
mtd device names.

When CFI MTD NOR device are supported, the spi-nor index is chosen after
the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS.

When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config
is replaced by to cfi_flash_num_flash_banks in the include file
mtd/cfi_flash.h.

This generic name "nor%d" can be use to identify the mtd spi-nor device
without knowing the real device name or the DT path of the device,
used with API get_mtd_device_nm() and is used in mtdparts command.

This patch also avoids issue when the same NOR device is present 2 times,
for example on STM32MP15F-EV1:

STM32MP&gt; mtd list
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \
total 64 MiB

List of MTD devices:
* nand0
  - type: NAND flash
  - block size: 0x40000 bytes
  - min I/O: 0x1000 bytes
  - OOB size: 224 bytes
  - OOB available: 118 bytes
  - ECC strength: 8 bits
  - ECC step size: 512 bytes
  - bitflip threshold: 6 bits
  - 0x000000000000-0x000040000000 : "nand0"
* mx66l51235l
  - device: mx66l51235l@0
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@0
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"
* mx66l51235l
  - device: mx66l51235l@1
  - parent: spi@58003000
  - driver: jedec_spi_nor
  - path: /soc/spi@58003000/mx66l51235l@1
  - type: NOR flash
  - block size: 0x10000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "mx66l51235l"

The same mtd name "mx66l51235l" identify the 2 instances
mx66l51235l@0 and mx66l51235l@1.

This patch fixes a ST32CubeProgrammer / stm32prog command issue
with nor0 target on STM32MP157C-EV1 board introduced by
commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when
DM is enabled").

Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled")
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
[trini: Add &lt;dm/device.h&gt; to &lt;mtd.h&gt; for DM_MAX_SEQ_STR]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-ids: Add XTX XT25F128B</title>
<updated>2021-08-12T01:34:11+00:00</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2021-08-05T08:26:41+00:00</published>
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<id>urn:sha1:674a9483096148999818f336ddd2755172bfee0c</id>
<content type='text'>
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Signed-off-by: Jon Lin &lt;jon.lin@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: Mask out fast read if not requested in DT</title>
<updated>2021-08-03T06:26:25+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-30T07:20:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=d008190920fbea4cd52b185e5191e6e0e5ae1f56'/>
<id>urn:sha1:d008190920fbea4cd52b185e5191e6e0e5ae1f56</id>
<content type='text'>
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.

If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.

[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()</title>
<updated>2021-08-03T06:23:16+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-30T07:20:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=87e7219f9c6a30709ddf97b602983386f1b4cccf'/>
<id>urn:sha1:87e7219f9c6a30709ddf97b602983386f1b4cccf</id>
<content type='text'>
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.

The flash's hwcaps needs to be AND'ed before checking.

Fixes: 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-ids: Add support for XMC XM25QH64C</title>
<updated>2021-08-03T06:16:13+00:00</updated>
<author>
<name>Reto Schneider</name>
<email>reto.schneider@husqvarnagroup.com</email>
</author>
<published>2021-06-17T16:26:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=9102cce7f439b1939e37d28bfa587d316d1c7a73'/>
<id>urn:sha1:9102cce7f439b1939e37d28bfa587d316d1c7a73</id>
<content type='text'>
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.

Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider &lt;reto.schneider@husqvarnagroup.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-ids: Add support for Macronix MX25V8035F and MX25R1635F</title>
<updated>2021-07-10T13:59:20+00:00</updated>
<author>
<name>Frieder Schrempf</name>
<email>frieder.schrempf@kontron.de</email>
</author>
<published>2021-06-07T12:36:41+00:00</published>
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<id>urn:sha1:2a7977506915dba43c4dfe56b3054041881bfc2f</id>
<content type='text'>
The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very
similar, but has twice the size (16Mb) and supports a wider supply
voltage range.

They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs.

Signed-off-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
</content>
</entry>
<entry>
<title>dm: define LOG_CATEGORY for all uclass</title>
<updated>2021-07-06T16:38:03+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-04-27T09:02:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=b953ec2bca1ebe059366e870eb4bec5e7af9c36b'/>
<id>urn:sha1:b953ec2bca1ebe059366e870eb4bec5e7af9c36b</id>
<content type='text'>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t</title>
<updated>2021-06-29T13:46:54+00:00</updated>
<author>
<name>Takahiro Kuwano</name>
<email>Takahiro.Kuwano@infineon.com</email>
</author>
<published>2021-06-29T06:01:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=5b8ec59e2a219185127fcaa640c2f5d5aba3acd6'/>
<id>urn:sha1:5b8ec59e2a219185127fcaa640c2f5d5aba3acd6</id>
<content type='text'>
Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.

Signed-off-by: Takahiro Kuwano &lt;Takahiro.Kuwano@infineon.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
</feed>
