StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror) https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP 2023-11-29T02:47:53+00:00 2023-11-29T02:47:53+00:00 Hal Feng hal.feng@starfivetech.com 2023-08-17T02:17:28+00:00 urn:sha1:7a6dd69c9d1591c564ec7f516989aad3a9c3d7ce Make the code be compatible with the StarFive VisionFive 2 board. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> 2023-07-26T08:03:44+00:00 William Qiu william.qiu@starfivetech.com 2023-07-17T06:45:18+00:00 urn:sha1:f9516d9db115e5067079f823d2c4ad9938bd174e fix mmc device power-up sequence. Signed-off-by: William Qiu <william.qiu@starfivetech.com> 2023-07-26T08:03:40+00:00 William Qiu william.qiu@starfivetech.com 2023-07-17T06:36:43+00:00 urn:sha1:8bc74ce3e17fc569c612f4f1c70d1be4c94475f5 Add tuning and other related code to the driver to support HS200 mode. Signed-off-by: William Qiu <william.qiu@starfivetech.com> 2021-09-13T23:02:10+00:00 Andre Przywara andre.przywara@arm.com 2021-09-03T15:49:16+00:00 urn:sha1:0b508ca821d383b2fd68f4b581cf606e329fff36 Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the FIFO is completely full: the level size reads as zero, but the FIFO_FULL bit is set. We won't do a single iteration of the read loop in this case, so will be stuck forever. Check for this situation and use a safe minimal FIFO size instead when we hit this case. This fixes MMC boot on A20 devices after the MMC FIFO optimisation (9faae5457f52). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> 2021-09-13T03:46:50+00:00 Michael Walle michael@walle.cc 2021-09-10T09:20:52+00:00 urn:sha1:285edfd7821e79de579b0bf1a7328dead2304a0b Since the beginning of this driver which was initially for the MPC8379 and MPC8536 SoCs, there is this spurious 1ms delay. According to the comment it should actually be only 8 clock cycles. Esp. during EFI block transfers, this 1ms add up to a significant delay and slows down EFI boot. I couldn't find any mention in the MPC8536 that there should be a delay of 8 clock cycles between commands. The SD card specification mentions that the clock has to be left enabled for 8 cycles after a command or response. But I don't see how this delay will help with this. Go ahead and just remove it. If there will ever be any regression we can introduce a compile time flag, but for now I'd like to keep it simple. In the split off imx driver this delay was also removed in commit 9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending command"). Signed-off-by: Michael Walle <michael@walle.cc> 2021-09-10T10:17:49+00:00 Ye Li ye.li@nxp.com 2021-08-17T09:20:34+00:00 urn:sha1:fb8c2e8fa936f8ebe4b7cc822abe33ff620585cd HS400_ES is missed when down grade to HS mode during device_remove the mmc device Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> 2021-09-10T10:17:41+00:00 Ye Li ye.li@nxp.com 2021-08-17T09:20:33+00:00 urn:sha1:3f4e52fc9d81e95ee90f6be7b05ca62fc8c7c1e3 When send_status is false or wait_dat0 is not supported, the switch function should not send CMD13 but directly return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> 2021-09-10T10:17:04+00:00 Aswath Govindraju a-govindraju@ti.com 2021-08-13T17:34:41+00:00 urn:sha1:19f7a34a4642e25aa8b80c6d75129fe7848a158d Add support for enumerating MMC card in a given mode using mmc rescan and mmc dev commands. The speed mode is provided as the last argument in these commands and is indicated using the index from enum bus_mode in include/mmc.h. A speed mode can be set only if it has already been enabled in the device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> 2021-09-10T10:13:34+00:00 Yuezhang.Mo@sony.com Yuezhang.Mo@sony.com 2021-03-17T06:44:37+00:00 urn:sha1:4a3ea75de4c5b3053eac326bf1c753ed65df8cb9 This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59. In eMMC specification, for the response-with-busy(R1b, R5b) command, the DAT0 will driven to LOW as BUSY status, and in sdhci specification, the transfer complete bit should be wait for BUSY status de-assert. All response-with-busy commands don't contain data, the data judgement is no need. Signed-off-by: Yuezhang.Mo <Yuezhang.Mo@sony.com> Reviewed-by: Andy Wu <Andy.Wu@sony.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> 2021-08-27T12:33:02+00:00 Tom Rini trini@konsulko.com 2021-08-27T12:33:02+00:00 urn:sha1:b9cb74a5aa256fc34a1b2b9dd847a985b91f34f6 Xilinx changes for v2021.10-rc3 xilinx: - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT zynq: - Wire single QSPI - Use power-source instead of io-standard properties - Enable nor on zc770-xm012 zynqmp: - Change handling around multi_boot() - Setup offset for u-boot.itb in spi - Generate run time dfu_alt_info for capsule update - Use explicit values for enums (zynqmp_firmware.h) - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command - Disable WDT driver by default - Bind usb/scsi via preboot because of EFI - DT updates/fixes - Add soc driver - Fix SPL SPI boot mode versal: - Add soc driver sdhci: - Update tap delay programming for zynq_sdhci driver cmd: - Fix RTC uclass handling in date command - Update pwm help message - Update reset help message watchdog: - Fix wwdt compilation rtc: - Deal with seq alias in rtc uclass - Add zynqmp RTC driver fdt: - Add kernel-doc for fdt_fixup_memory_banks()