starfive-tech/u-boot.git/drivers/ddr/imx, branch rtthread_AMP

ddr: Add DDR driver for iMX8ULP

2021-08-09T12:46:51+00:00

Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li

imx8mp: refine power on imx8mp board

2021-04-08T07:18:29+00:00

VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng Signed-off-by: Peng Fan

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42+00:00

Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include at all, so remove that include. Signed-off-by: Simon Glass Signed-off-by: Tom Rini

imx: ddr: imx8m: Move selfref_en after DDR scrub

2021-01-23T10:30:30+00:00

When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: Ye Li Acked-by: Peng Fan Signed-off-by: Peng Fan

imx8m: ddrphy_utils: Improve coding style

2020-07-27T12:02:28+00:00

Currently checkpatch is not happy about this file: total: 14 errors, 2 warnings, 7 checks, 359 lines checked Improve the coding style so that it can now report: total: 0 errors, 0 warnings, 6 checks, 360 lines checked Reported-by: Tom Rini Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini Reviewed-by: Peng Fan

drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue

2020-07-14T07:23:46+00:00

Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li Signed-off-by: Oliver Chen Signed-off-by: Jacky Bai Signed-off-by: Peng Fan

drivers: ddr: imx8mp: Add inline ECC feature support

2020-07-14T07:23:46+00:00

the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan

driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m

2020-07-14T07:23:46+00:00

The 'selfref_en' should be bit'0', so correct the setting to enable the auto self-refresh. Reviewed-by: Jian Li Reviewed-by: Ye Li Signed-off-by: Jacky Bai Signed-off-by: Peng Fan

driver: ddr: imx: skip ddr_ss_gpr config on imx8mn

2020-07-14T07:23:46+00:00

There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting this register on i.MX8MN. Signed-off-by: Jacky Bai Signed-off-by: Peng Fan

common: Drop log.h from common header

2020-05-19T01:19:18+00:00

Move this header out of the common header. Signed-off-by: Simon Glass