starfive-tech/u-boot.git/drivers/clk, branch rtthread_AMPStarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP2023-11-29T02:54:11+00:00clk: starfive: jh7110: Add full i2c clocks2023-11-29T02:54:11+00:00Hal Fenghal.feng@starfivetech.com2023-08-22T03:10:23+00:00urn:sha1:96ee0021ad55ae469d3f337f1995084c11b88c57
Correct the parent of i2c clocks and add full i2c clocks.
The code mainly is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
board: starfive: copyright: Standardize the copyright format2023-04-23T03:19:47+00:00Yanhong Wangyanhong.wang@starfivetech.com2023-04-23T03:19:47+00:00urn:sha1:fe8426ebb03dc13a06758d2c4c0571e19b3c064a
Unify the content format of the copyright section
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
clk: starfive: Add PCIe clocks for PCIe controller2023-02-22T09:54:41+00:00Mason Huomason.huo@starfivetech.com2023-02-01T03:04:21+00:00urn:sha1:84cf73607249e690ab2793e44697cc07985260cc
Add the stg clocks for PCIe controller.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
i2c:desigware-snps: add i2c clock config2023-02-17T03:59:52+00:00keith.zhaokeith.zhao@starfivetech.com2023-02-16T11:46:27+00:00urn:sha1:83dd8745566468e28ff72893c76eb5e7d69a8bf4
add clock config for i2c2 and i2c5
update the i2c driver clock config
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
clk:starfive: Add vout clock driver for StarFive JH71102023-01-05T10:04:26+00:00Yanhong Wangyanhong.wang@starfivetech.com2022-11-23T02:43:00+00:00urn:sha1:1b96445bfc9f35f55e8fead28ddfcc36325cc964
Add vout clock driver for StarFive JH7110
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
clk: starfive: jh7110: Modify the parameters of clk_register()2022-10-18T08:24:38+00:00Yan Hong Wangyanhong.wang@starfivetech.com2022-09-14T08:54:07+00:00urn:sha1:0c1fefaf48d0f58453dedda58dcd6ac206d7970f
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
clk:jh7110: update apb_bus clk relationship2022-10-18T08:24:37+00:00yanhong.wangyanhong.wang@starfivetech.com2022-08-03T07:59:08+00:00urn:sha1:20f3a9aeb57d6237a1a19ae519e23f06d98f88ef
The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
clk:jh7110: pll0 dynamically gets the frequency2022-10-18T08:24:37+00:00saminsamin.guo@starfivetech.com2022-06-13T07:25:05+00:00urn:sha1:d21940b4fcb226f80cec587794be4ca9e8c66a3f
pll0 dynamically gets the frequency.
Signed-off-by: samin <samin.guo@starfivetech.com>
clk:riscv:starfive: update uart3-uart5 clks2022-10-18T08:24:36+00:00yanhong.wangyanhong.wang@starfivetech.com2022-06-09T02:18:34+00:00urn:sha1:4806c43e7adae907b72eaedeb635fa2c03eef196
Update uart3-uart5 clks register info for StarFive JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
clk:starfive-jh7110: Update pll0/pll1/pll2 clk2022-10-18T08:24:36+00:00yanhong.wangyanhong.wang@starfivetech.com2022-05-25T05:38:00+00:00urn:sha1:0b2572d9978f265b51a218f334434ab9fde41552
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>