starfive-tech/u-boot.git/drivers/clk/ti, branch master

clk: ti: add am33xx/am43xx spread spectrum clock support

2021-10-11T18:27:32+00:00

The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Dario Binacchi

clk: ti: k3: Update driver to account for divider flags

2021-09-17T18:47:03+00:00

The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach

clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write

2021-09-17T18:47:03+00:00

There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach

clk: add support for TI K3 SoC clocks

2021-06-11T11:04:52+00:00

Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo

clk: add support for TI K3 SoC PLL

2021-06-11T11:04:52+00:00

Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo

clk: sci-clk: fix return value of set_rate

2021-06-11T11:04:52+00:00

Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo

clk: ti: am3-dpll: use custom API for memory access

2021-05-12T10:57:57+00:00

Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi

clk: ti: gate: use custom API for memory access

2021-05-12T10:57:57+00:00

Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi

clk: ti: change clk_ti_latch() signature

2021-05-12T10:57:57+00:00

The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi

clk: ti: add custom API for memory access

2021-05-12T10:57:57+00:00

As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi