<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/drivers/clk/sunxi, branch master</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-10-25T13:54:06+00:00</updated>
<entry>
<title>clk: sunxi: Extend DM_RESET selection to SPL</title>
<updated>2021-10-25T13:54:06+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-09-11T19:45:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=e0c628d728d6f2b0ab01488706b1a9679512a982'/>
<id>urn:sha1:e0c628d728d6f2b0ab01488706b1a9679512a982</id>
<content type='text'>
The sunxi clock driver exposes a reset controller, so it selects the
reset controller framework. Ensure that dependency is also satisfied
when building the driver for the SPL.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Add drivers for A31 and H6 PRCM CCUs</title>
<updated>2021-10-11T09:46:44+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-09-12T14:47:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=23c83366f326fb88dd4ec40315ebae14df55ebc0'/>
<id>urn:sha1:23c83366f326fb88dd4ec40315ebae14df55ebc0</id>
<content type='text'>
Add a driver so the clocks/resets for these peripherals (especially I2C,
RSB, and UART) can be enabled using the normal uclass methods.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Add support for I2C gates/resets</title>
<updated>2021-10-11T09:46:44+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-09-12T14:47:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c61897bf029e86a46cdba53ced48889eae1cd468'/>
<id>urn:sha1:c61897bf029e86a46cdba53ced48889eae1cd468</id>
<content type='text'>
Currently, the I2C clocks are configured in the sunxi board code. Add
the I2C clocks to the DM clock driver so they can be enabled from the
DM I2C driver using the normal uclass methods.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Move header out of arch directory</title>
<updated>2021-10-11T09:46:44+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-09-12T16:48:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=21d314a6612564ee202d8a8189ed37d5c6abf0dd'/>
<id>urn:sha1:21d314a6612564ee202d8a8189ed37d5c6abf0dd</id>
<content type='text'>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: h6: Add XHCI clocks</title>
<updated>2021-04-16T00:12:59+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-02-08T05:57:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=fa7eabf650ae8ad904b1258f1dd6bcc02922bafe'/>
<id>urn:sha1:fa7eabf650ae8ad904b1258f1dd6bcc02922bafe</id>
<content type='text'>
The XHCI controller has its own clock and reset. Add them.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Add a dummy clock driver for the RTC</title>
<updated>2021-04-16T00:12:59+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-02-08T05:57:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=9078b67f3c968cbc3142432decc93a51780b4642'/>
<id>urn:sha1:9078b67f3c968cbc3142432decc93a51780b4642</id>
<content type='text'>
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is
used, among other things, by the XHCI controller in the H6. To be able
to call clk_get_bulk() on the XHCI controller, some device needs to
provide all referenced clocks.

Since LOSC is a fixed-rate always-on clock, implementation is trivial.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Add support for H616 clocks</title>
<updated>2021-01-25T21:52:01+00:00</updated>
<author>
<name>Jernej Skrabec</name>
<email>jernej.skrabec@siol.net</email>
</author>
<published>2021-01-11T20:11:52+00:00</published>
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<id>urn:sha1:1dc70ffa1cd9057e9c70d15b9c8aea2779854c74</id>
<content type='text'>
This commit introduces DM H616 clock driver.

Signed-off-by: Jernej Skrabec &lt;jernej.skrabec@siol.net&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename auto_alloc_size members to be shorter</title>
<updated>2020-12-13T15:00:25+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:17+00:00</published>
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<id>urn:sha1:41575d8e4c334df148c4cdd7c40cc825dc0fcaa1</id>
<content type='text'>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: add compatible string for V3</title>
<updated>2020-11-17T00:42:21+00:00</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2020-10-26T14:18:02+00:00</published>
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<id>urn:sha1:6ffdc43cc5e6070edf91bac653cc8a0449dbe545</id>
<content type='text'>
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.

Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/bitops.h from common header</title>
<updated>2020-05-19T01:19:23+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=cd93d625fd751d55c729c78b10f82109d56a5f1d'/>
<id>urn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
