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<title>starfive-tech/u-boot.git/doc/board/openpiton, branch master</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-07-24T08:49:51+00:00</updated>
<entry>
<title>doc: fix board/openpiton/riscv64.rst</title>
<updated>2021-07-24T08:49:51+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2021-07-24T08:43:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=1364029263a34924fa9bb7126a436d3ed562b7e7'/>
<id>urn:sha1:1364029263a34924fa9bb7126a436d3ed562b7e7</id>
<content type='text'>
* remove duplicate heading to avoid build error with 'make htmldocs'
* length of underlines must match header
* use appropriate header levels
* fix type %s/linux/Linux/

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>board: riscv: add openpiton-riscv64 SoC support</title>
<updated>2021-07-06T05:50:56+00:00</updated>
<author>
<name>Tianrui Wei</name>
<email>tianrui-wei@outlook.com</email>
</author>
<published>2021-07-01T04:54:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=8a44fe69439438797b93b2e7dd70e1a8fad31519'/>
<id>urn:sha1:8a44fe69439438797b93b2e7dd70e1a8fad31519</id>
<content type='text'>
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl-&gt;u-boot SPL-&gt;
opensbi-&gt;u-boot proper-&gt;Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper

Signed-off-by: Tianrui Wei &lt;tianrui-wei@outlook.com&gt;
Signed-off-by: Jonathan Balkind &lt;jbalkind@ucsb.edu&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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