StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror) https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master 2021-11-16T14:51:04+00:00 2021-11-16T14:51:04+00:00 Tom Rini trini@konsulko.com 2021-11-16T14:51:04+00:00 urn:sha1:2ffa0e87df3a7595f71d05782924ee83146d9fe7 Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts 2021-11-15T14:59:33+00:00 Ricardo Salveti ricardo@foundries.io 2021-11-04T19:28:02+00:00 urn:sha1:11c0255cd8a7177e2b714040efcfd51844cb5d8e Config check should be done without the SPL_ prefix. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Link: https://lore.kernel.org/r/20211104192802.3093811-1-ricardo@foundries.io Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2021-10-29T11:01:47+00:00 Michal Simek michal.simek@xilinx.com 2021-10-21T06:58:50+00:00 urn:sha1:412ab133286af968732c2ff3cc2b615e078d8da1 Fix issue reported by checkpatch.pl WARNING: Possible comma where semicolon could be used #499: FILE: board/xilinx/zynqmp/zynqmp.c:499: + size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/ef264451ef9455ada9784bedbc91f74b94b8a237.1634799528.git.michal.simek@xilinx.com 2021-10-29T11:00:52+00:00 Michal Simek michal.simek@xilinx.com 2021-10-25T08:10:52+00:00 urn:sha1:e8b43c6409a064429285e8c2bf6e1a27879f995a Save multiboot register as u-boot variable. And use it as primary source for composing dfu_alt_info for capsule update. If variable is not defined Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Link: https://lore.kernel.org/r/96556221443489c952717bcb340b4707901c9bdd.1635149450.git.michal.simek@xilinx.com 2021-10-27T20:38:26+00:00 Ilias Apalodimas ilias.apalodimas@linaro.org 2021-10-26T06:12:33+00:00 urn:sha1:e7fb789612e39653f9f20ad08ad40896c7f61742 OF_HOSTFILE is used on sandbox configs only. Although it's pretty unique and not causing any confusions, we are better of having simpler config options for the DTB. So let's replace that with the existing OF_BOARD. U-Boot would then have only three config options for the DTB origin. - OF_SEPARATE, build separately from U-Boot - OF_BOARD, board specific way of providing the DTB - OF_EMBED embedded in the u-boot binary(should not be used in production Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> 2021-10-21T06:56:41+00:00 Michal Simek michal.simek@xilinx.com 2021-10-18T12:02:15+00:00 urn:sha1:60705883d245c135f20660ebc7e2ed20c294387a There is no need to use u-boot.itb as name when this is already recorded in CONFIG_SPL_FS_LOAD_PAYLOAD_NAME macro. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Link: https://lore.kernel.org/r/38a236ed317510c26b37525da0e7bc26b411222c.1634558534.git.michal.simek@xilinx.com 2021-10-21T06:55:46+00:00 Michal Simek michal.simek@xilinx.com 2021-10-18T11:30:04+00:00 urn:sha1:f510927d55e44bc06a742cd774515197b5c6c128 Now intentional fallthrough in switch-case should be labelled that's why convert comment. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Link: https://lore.kernel.org/r/b3e976bd3b9bbe7061fec5ba0a3b4e78fdd78394.1634556602.git.michal.simek@xilinx.com 2021-10-21T06:51:33+00:00 Michal Simek michal.simek@xilinx.com 2021-10-14T17:07:52+00:00 urn:sha1:d2d14383bae4732c11b68c14aa33cf7b9f3bf40c DLC21 is used as fast jtag cable. The patch adds support for this board from PS perspective. The most interesting part on the board is seps525 oled display. Also i2c, gpio, ethernet, uart, SD and eMMC are tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3d35cd6a11cffc7456e21a88b214cc965734e852.1634231268.git.michal.simek@xilinx.com 2021-10-21T06:51:00+00:00 Jorge Ramirez-Ortiz jorge@foundries.io 2021-10-13T13:48:00+00:00 urn:sha1:398a74ae330dfc4e46744874ebbe5394d2679c37 When boot.bin is configured for secure boot the CSU will disable the JTAG interface on all cases. Some boards might rely on this interface for flashing to QSPI in which case those systems might end up bricked during development. This commit will restore the interface under CSU control Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Link: https://lore.kernel.org/r/20211013134800.19452-1-jorge@foundries.io Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2021-09-30T15:29:41+00:00 Tom Rini trini@konsulko.com 2021-09-30T15:29:41+00:00 urn:sha1:8bef03683623d6a7adfff1f859ed44fad9e92ed7 Xilinx changes for v2022.01-rc1 zynq: - Enable capsule update for qspi and mmc - Update zed DT qspi compatible string zynqmp: - Add missing modeboot for EMMC - Add missing nand DT properties - List all eeproms for SC on vck190 - Add vck190 SC psu_init clk: - Handle only GATE type clock for Versal watchdog: - Update versal driver to handle system reset