<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/board/seeed, branch master</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-06-09T11:34:18+00:00</updated>
<entry>
<title>imx: Add SeeedStudio NPI-IMX6ULL Support</title>
<updated>2021-06-09T11:34:18+00:00</updated>
<author>
<name>Navin Sankar Velliangiri</name>
<email>navin@linumiz.com</email>
</author>
<published>2021-05-18T03:33:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=a3a0bc85c0501c2374966104b8daca6c69101625'/>
<id>urn:sha1:a3a0bc85c0501c2374966104b8daca6c69101625</id>
<content type='text'>
CPU:   Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 49C
Reset cause: POR
Model: Seeed NPi iMX6ULL Dev Board with NAND
Board: Seeed NPi i.MX6ULL Dev Board
DRAM:  512 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial@2020000
Out:   serial@2020000
Err:   serial@2020000
Net:   FEC0

Working:
- Eth0
- MMC/SD
- NAND
- UART 1
- USB host

Signed-off-by: Navin Sankar Velliangiri &lt;navin@linumiz.com&gt;

Note:

Changes in v2:

 * removed unnecessary space in imx6ull-seeed-npi-imx6ull-dev-board.dts file.
 * Used SZ_2M for CONFIG_SYS_MALLOC_LEN size allocation.
</content>
</entry>
<entry>
<title>common: Drop linux/bitops.h from common header</title>
<updated>2020-05-19T01:19:23+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=cd93d625fd751d55c729c78b10f82109d56a5f1d'/>
<id>urn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop init.h from common header</title>
<updated>2020-05-18T21:33:33+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=691d719db7183dfb1d1360efed4c5e9f6899095f'/>
<id>urn:sha1:691d719db7183dfb1d1360efed4c5e9f6899095f</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mips: mt76xx: linkit-smart-7688: Use ioremap_nocache to get address</title>
<updated>2018-11-18T15:02:23+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-10-09T06:59:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=8bd197770621df19e3eacd3ef83f9616b15b126f'/>
<id>urn:sha1:8bd197770621df19e3eacd3ef83f9616b15b126f</id>
<content type='text'>
Use the correct function to get the uncached address to access the SoC
registers.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MAINTAINERS: Update some entries for missed boards</title>
<updated>2018-09-30T17:00:37+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-09-30T14:24:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=2c1e16b9d2e3a6138acf4ffd9866e47ddbe6d453'/>
<id>urn:sha1:2c1e16b9d2e3a6138acf4ffd9866e47ddbe6d453</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mips: Add LinkIt Smart 7688 support</title>
<updated>2018-09-23T12:27:19+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-08-16T13:27:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=b02f76a83541fe9fe3a2918039b26fc133699c17'/>
<id>urn:sha1:b02f76a83541fe9fe3a2918039b26fc133699c17</id>
<content type='text'>
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM
and 32 MiB of flash (SPI NOR).

This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
[fixed and regenerated defconfig files]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
</feed>
