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<title>starfive-tech/u-boot.git/arch/xtensa/include/asm/string.h, branch visionfive_devel</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=visionfive_devel</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=visionfive_devel'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2016-08-15T22:46:38+00:00</updated>
<entry>
<title>xtensa: add support for the xtensa processor architecture [2/2]</title>
<updated>2016-08-15T22:46:38+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2016-08-10T15:36:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c978b52410016b0ab5a213f235596340af8d45f7'/>
<id>urn:sha1:c978b52410016b0ab5a213f235596340af8d45f7</id>
<content type='text'>
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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