<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/arch/x86/lib, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-08-03T01:35:50+00:00</updated>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-x86</title>
<updated>2021-08-03T01:35:50+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-03T01:35:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=3b64774323298362f9833aac75bb4639b4f98999'/>
<id>urn:sha1:3b64774323298362f9833aac75bb4639b4f98999</id>
<content type='text'>
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
</content>
</entry>
<entry>
<title>global: Convert simple_strtoul() with hex to hextoul()</title>
<updated>2021-08-02T17:32:14+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-07-24T15:03:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=7e5f460ec457fe310156e399198a41eb0ce1e98c'/>
<id>urn:sha1:7e5f460ec457fe310156e399198a41eb0ce1e98c</id>
<content type='text'>
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.

Add a proper comment to simple_strtoul() while we are here.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE</title>
<updated>2021-08-02T16:01:38+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-08-02T09:45:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=33e4ab31a9647b0bacd44b579199eaae239d69e3'/>
<id>urn:sha1:33e4ab31a9647b0bacd44b579199eaae239d69e3</id>
<content type='text'>
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.

Move board_final_cleanup() to fsp2 directory.

Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Don't program MTRR for DRAM for FSP1</title>
<updated>2021-08-02T16:01:29+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-08-02T09:45:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=02541601cbc4adbb9a65b68faa9b8ce14dac7f1d'/>
<id>urn:sha1:02541601cbc4adbb9a65b68faa9b8ce14dac7f1d</id>
<content type='text'>
There are several outstanding issues as to why this does not apply
to FSP1:

* For FSP1, the system memory and reserved memory used by FSP are
  already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
  same RES_MEM_RESERVED resource type. Its address is programmed
  and reported by FSP to be near the top of 4 GiB space, which is
  not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
  to be exactly the power of 2. This causes reserved bits of the
  IA32_MTRR_PHYSMASK register to be written which generates #GP.

For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>smbios: error handling for invalid addresses</title>
<updated>2021-07-24T08:49:51+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2021-05-15T16:07:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c193d9bd284565df4ddcdd1e9190d2ce718e9eb7'/>
<id>urn:sha1:c193d9bd284565df4ddcdd1e9190d2ce718e9eb7</id>
<content type='text'>
SMBIOS tables only support 32bit addresses. If we don't have memory here
handle the error gracefully:

* on x86_64 fail to start U-Boot
* during UEFI booting ignore the missing table

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Ensure the e820 map is installed in all cases</title>
<updated>2021-07-15T11:56:16+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-07-11T03:15:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=2f91fc40039d2ef6f433d5c56c4f4701975f510f'/>
<id>urn:sha1:2f91fc40039d2ef6f433d5c56c4f4701975f510f</id>
<content type='text'>
This is a revert of a recent logic change in setup_zimage(). We do
actually need to install this information always. Change it to install
from the Coreboot tables if available, else the normal source.

Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot")
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Do cache set-up by default when booting from coreboot</title>
<updated>2021-07-15T11:50:09+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-06-27T23:51:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=7052968707b2c16da6b9c43aa058435d2932eb82'/>
<id>urn:sha1:7052968707b2c16da6b9c43aa058435d2932eb82</id>
<content type='text'>
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.

If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is used</title>
<updated>2021-07-07T14:17:54+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-07T07:36:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=cfa5189811e29e4a24ed41a814e2feb41e79b52e'/>
<id>urn:sha1:cfa5189811e29e4a24ed41a814e2feb41e79b52e</id>
<content type='text'>
With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.

At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.

With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.

Drop the emulator definition when CONFIG_BIOSEMU is used.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>treewide: Convert macro and uses of __section(foo) to __section("foo")</title>
<updated>2021-05-24T18:21:30+00:00</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:23:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=236f2ec43266cb4dabd320381498df6c9d80c82d'/>
<id>urn:sha1:236f2ec43266cb4dabd320381498df6c9d80c82d</id>
<content type='text'>
This commit does the same thing as Linux commit 33def8498fdd.

Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>cpu: Rename SPL_CPU_SUPPORT to SPL_CPU</title>
<updated>2021-03-27T02:04:31+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:11:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=529d5f96cf7be9ae60db1a5f1c2a2aa0a3d5d26d'/>
<id>urn:sha1:529d5f96cf7be9ae60db1a5f1c2a2aa0a3d5d26d</id>
<content type='text'>
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.

Tidy up the TODO that prompted this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
