<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/arch/x86/lib/fsp, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-08-02T16:01:38+00:00</updated>
<entry>
<title>x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE</title>
<updated>2021-08-02T16:01:38+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-08-02T09:45:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=33e4ab31a9647b0bacd44b579199eaae239d69e3'/>
<id>urn:sha1:33e4ab31a9647b0bacd44b579199eaae239d69e3</id>
<content type='text'>
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.

Move board_final_cleanup() to fsp2 directory.

Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Don't program MTRR for DRAM for FSP1</title>
<updated>2021-08-02T16:01:29+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-08-02T09:45:21+00:00</published>
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<id>urn:sha1:02541601cbc4adbb9a65b68faa9b8ce14dac7f1d</id>
<content type='text'>
There are several outstanding issues as to why this does not apply
to FSP1:

* For FSP1, the system memory and reserved memory used by FSP are
  already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
  same RES_MEM_RESERVED resource type. Its address is programmed
  and reported by FSP to be near the top of 4 GiB space, which is
  not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
  to be exactly the power of 2. This causes reserved bits of the
  IA32_MTRR_PHYSMASK register to be written which generates #GP.

For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Don't enable FSP graphics if booted from coreboot</title>
<updated>2021-03-27T02:04:30+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=937175ee72fa5318016be3d887bd1a1b5409f038'/>
<id>urn:sha1:937175ee72fa5318016be3d887bd1a1b5409f038</id>
<content type='text'>
This driver cannot work when booted from coreboot, since the FSP
information is not available. Disable it in that case, so that the
coreboot video driver can be used instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop asm/global_data.h from common header</title>
<updated>2021-02-02T20:33:42+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-31T03:38:53+00:00</published>
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<id>urn:sha1:401d1c4f5d2d29c4bc4beaec95402ca23eb63295</id>
<content type='text'>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename ..._platdata variables to just ..._plat</title>
<updated>2020-12-13T23:51:09+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=8a8d24bdf174851ebb8607f359d54b72e3283b97'/>
<id>urn:sha1:8a8d24bdf174851ebb8607f359d54b72e3283b97</id>
<content type='text'>
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename 'platdata' variables to just 'plat'</title>
<updated>2020-12-13T23:51:08+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=caa4daa2ae3dc0a3e516addea5772c9af76abcb0'/>
<id>urn:sha1:caa4daa2ae3dc0a3e516addea5772c9af76abcb0</id>
<content type='text'>
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Adjust calculations for MTRR range and DRAM top</title>
<updated>2020-11-06T01:51:33+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-11-04T16:57:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=d46c0932a9d4b2fcd8064f4567436f5143526147'/>
<id>urn:sha1:d46c0932a9d4b2fcd8064f4567436f5143526147</id>
<content type='text'>
At present the top of available DRAM is the same as the top of the range
of the low-memory MTRR.

In fact, U-Boot is allowed to use memory up until the start of the FSP
reserved memory. Use that value for low_end, since it makes more memory
available.

Keep the same calculation as before for mtrr_top, i.e. the top of
reserved memory.

A side-effect of this change is that the E820 tables have a single entry
that extends from the bottom of the memory used by U-Boot to the bottom
of the FSP reserved memory. This includes the bloblist, if ACPI tables
are placed there.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Silence some logging statements</title>
<updated>2020-11-06T01:51:32+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-11-04T16:57:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=1da448bb9fd281e5a0574aab838d9ef1f6b18575'/>
<id>urn:sha1:1da448bb9fd281e5a0574aab838d9ef1f6b18575</id>
<content type='text'>
Quite a few log_info() calls are included in the x86 code which should use
log_debug() instead. Convert them to reduce unwanted output.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a way to add to the e820 memory table</title>
<updated>2020-09-25T03:27:25+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-09-22T18:45:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=70c202c480b8dadd27dbfb723f0cede1fb0e0d0c'/>
<id>urn:sha1:70c202c480b8dadd27dbfb723f0cede1fb0e0d0c</id>
<content type='text'>
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Notify the FSP of the 'end firmware' event</title>
<updated>2020-09-25T03:27:22+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-09-22T18:45:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=7c73cea44290a5779bfcaafe6d7a1dbf6fbc1b1d'/>
<id>urn:sha1:7c73cea44290a5779bfcaafe6d7a1dbf6fbc1b1d</id>
<content type='text'>
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.

Currently this causes a crash with the APL FSP, so leave it disabled for
now.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
