<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/arch/x86/include/asm, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2021-09-22T13:50:35+00:00</updated>
<entry>
<title>x86: tangier: acpi: Add GPIO card detection to SDHCI #2</title>
<updated>2021-09-22T13:50:35+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2021-09-11T18:27:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=57e2c0a86fe48194c9407d36d60f9ab033b4460e'/>
<id>urn:sha1:57e2c0a86fe48194c9407d36d60f9ab033b4460e</id>
<content type='text'>
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>efi_loader rename enum efi_mem_type to efi_memory_type</title>
<updated>2021-08-17T15:24:08+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2021-08-17T13:02:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c91737b7f1a5180b8944eea2121347ef6429b17c'/>
<id>urn:sha1:c91737b7f1a5180b8944eea2121347ef6429b17c</id>
<content type='text'>
Use the same name as in the UEFI specification to avoid confusion.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>x86: mtrr: Abort if requested size is not power of 2</title>
<updated>2021-08-02T07:11:41+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-31T08:45:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=9a7c6fde07d04e392dadfd406b7837c04aed0d72'/>
<id>urn:sha1:9a7c6fde07d04e392dadfd406b7837c04aed0d72</id>
<content type='text'>
The size parameter of mtrr_add_request() and mtrr_set_next_var()
shall be power of 2, otherwise the logic creates a mask that does
not meet the requirement of IA32_MTRR_PHYSMASK register.

Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add function comments to cb_sysinfo.h</title>
<updated>2021-07-15T11:50:17+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-06-27T23:51:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c5c62155c542368269d7a0e968401e76abcc2490'/>
<id>urn:sha1:c5c62155c542368269d7a0e968401e76abcc2490</id>
<content type='text'>
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Update the MP constants to avoid conflicts</title>
<updated>2021-07-15T11:50:04+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-06-27T23:51:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=0f5ca1d1f1d399191d6481d1c8853c9ca6fe25ff'/>
<id>urn:sha1:0f5ca1d1f1d399191d6481d1c8853c9ca6fe25ff</id>
<content type='text'>
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.

Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.

This fixes the 'mtrr' command when CONFIG_SMP is not enabled.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>lmb: move CONFIG_LMB in Kconfig</title>
<updated>2021-04-22T18:09:45+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-03-10T09:16:25+00:00</published>
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<id>urn:sha1:77b8cfef531f7758f35a8598bd474713cfc2c2ec</id>
<content type='text'>
Migrate CONFIG_LMB in Kconfig.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>x86: mtrr: Fix function descriptions</title>
<updated>2021-04-15T02:43:17+00:00</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2021-03-23T09:39:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=21296b093e90d9dbe99b7b23bc9dcad79d824034'/>
<id>urn:sha1:21296b093e90d9dbe99b7b23bc9dcad79d824034</id>
<content type='text'>
Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set().

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: coral: Allow init of debug UART in U-Boot proper</title>
<updated>2021-03-27T02:04:30+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=51de94dfe497b150c066788a38e93bd989ae7552'/>
<id>urn:sha1:51de94dfe497b150c066788a38e93bd989ae7552</id>
<content type='text'>
At present the debug UART is only set up in SPL, on the assumption that
the boot flow will always pass through there. When booting from coreboot,
SPL is not used, so the debug UART is not available.

Move the code into a common place so that it can be used in U-Boot proper
also. Add the required init to start_from_spl.S as well.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Allow installing an e820 when booting from coreboot</title>
<updated>2021-03-27T02:04:29+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=e7bae8283fea94cf470542916a063182c9e5771a'/>
<id>urn:sha1:e7bae8283fea94cf470542916a063182c9e5771a</id>
<content type='text'>
Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Update parsing of the latest sysinfo</title>
<updated>2021-03-27T00:59:59+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=1058ab37f7176370e835d53299c2ae44437925e3'/>
<id>urn:sha1:1058ab37f7176370e835d53299c2ae44437925e3</id>
<content type='text'>
Quite a few new tag types have been added over the years. Bring these into
U-Boot so that all required tags can be parsed.

Add a proper comment to struct sysinfo_t while we are here, since many of
the meanings are not obvious.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
