StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror) https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP 2020-07-17T06:32:24+00:00 2020-07-17T06:32:24+00:00 Simon Glass sjg@chromium.org 2020-07-10T00:43:17+00:00 urn:sha1:0990c894cc2e8e94a2b049e4c83d484d0b3afd9c With DDR4, Intel SOCs take quite a long time to init their memory. During this time, if the user is watching, it looks like SPL has hung. Add a message in this case. This works by adding a return code to fspm_update_config() that indicates whether MRC data was found and a new property to the device tree. Also add one more debug message while starting. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2019-12-15T03:44:16+00:00 Simon Glass sjg@chromium.org 2019-12-07T04:42:18+00:00 urn:sha1:cf87d3b5039d2e497380ccddff905cf3e58e0032 Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>