<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/arch/x86/cpu/Makefile, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2020-07-20T01:46:46+00:00</updated>
<entry>
<title>x86: Don't enable SMP in SPL</title>
<updated>2020-07-20T01:46:46+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-07-17T14:48:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=3d734b59c7c11021b5c92d147f86b1030ad35b16'/>
<id>urn:sha1:3d734b59c7c11021b5c92d147f86b1030ad35b16</id>
<content type='text'>
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL.
For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot,
but this is somewhat more complicated. For now that is disabled too.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Allow building an SPL image</title>
<updated>2020-05-04T07:28:28+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-01T03:21:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=b4d4f592b243d08791ce582073710444ede48446'/>
<id>urn:sha1:b4d4f592b243d08791ce582073710444ede48446</id>
<content type='text'>
Make a few adjustments to allow us to build an SPL image for coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add support for ACPI general-purpose events</title>
<updated>2020-02-07T14:46:35+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-06T16:55:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=e85cbe8b34147126cdd5dab09f4c745157f6083c'/>
<id>urn:sha1:e85cbe8b34147126cdd5dab09f4c745157f6083c</id>
<content type='text'>
ACPI GPEs are used to signal interrupts from peripherals that are accessed
via ACPI. In U-Boot these are modelled as interrupts using a separate
interrupt controller. Configuration is via the device tree.

Add a simple driver for this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: apl: Add Kconfig and Makefile</title>
<updated>2019-12-15T03:44:29+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-09T00:40:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=1fc541931461e039802868a8d2125add2acb5120'/>
<id>urn:sha1:1fc541931461e039802868a8d2125add2acb5120</id>
<content type='text'>
Add basic plumbing to allow Apollo Lake support to be used.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move qemu CPU fixup function into its own file</title>
<updated>2019-12-15T03:44:25+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=baaeb92c21370cc4717d4841906677f95ece55a3'/>
<id>urn:sha1:baaeb92c21370cc4717d4841906677f95ece55a3</id>
<content type='text'>
This function is specific to qemu so it seems best to keep it separate
from the generic code.

Move it out to a new file and update the condition to use if() instead of
 #ifdef

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Allow interrupt to happen once</title>
<updated>2019-12-15T03:44:16+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=592434139bf943cbc6c80f1467221904a3c917ec'/>
<id>urn:sha1:592434139bf943cbc6c80f1467221904a3c917ec</id>
<content type='text'>
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: cpu: Don't include the cpu driver in TPL</title>
<updated>2019-10-08T05:57:49+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=b377ebbd5b8fc371b0b27dd3551f2cc3718757dc'/>
<id>urn:sha1:b377ebbd5b8fc371b0b27dd3551f2cc3718757dc</id>
<content type='text'>
We don't need this driver very early in boot and it adds code size. Drop
it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add new slimbootloader CPU type</title>
<updated>2019-08-09T14:24:02+00:00</updated>
<author>
<name>Park, Aiden</name>
<email>aiden.park@intel.com</email>
</author>
<published>2019-08-03T08:30:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=544293f87850b415721690533dae2d27f77f44f3'/>
<id>urn:sha1:544293f87850b415721690533dae2d27f77f44f3</id>
<content type='text'>
This slimbootloader CPU type is to enable U-Boot as a payload which
runs on top of Slim Bootloader (https://github.com/slimbootloader).
The Slim Bootloader is designed with multi-stage architecture for
the execution from reset vector to OS booting, and supports QEMU,
Apollolake, Whiskeylake and Coffeelake platforms consuming Intel
FSP (https://github.com/IntelFsp) for silicon initialization
including CAR and memory initialization.
The Slim Bootloader generates new HOB (Hand Off Block) which are
serial port info, memory map info, performance data info and so on,
and passes it to a Payload. U-Boot as a payload will use these HOB
information for basic initialization such as serial console.

As an initial commit,
- Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type
- Add new arch/x86/cpu/slimbootloader directory with minimum codes
- Get hob_list pointer from Slim Bootloader

Signed-off-by: Aiden Park &lt;aiden.park@intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add support for starting from SPL/TPL</title>
<updated>2019-05-08T05:02:13+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-04-26T03:58:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=051c31b7a49933f25bcf2ffe8c7764642fcff0d4'/>
<id>urn:sha1:051c31b7a49933f25bcf2ffe8c7764642fcff0d4</id>
<content type='text'>
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.

Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: make the LAPIC / IOAPIC construct switchable with Kconfig</title>
<updated>2018-12-10T02:12:29+00:00</updated>
<author>
<name>Hannes Schmelzer</name>
<email>oe5hpm@oevsv.at</email>
</author>
<published>2018-11-18T22:19:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=da4cfa6b442809fc99a6b75255a99eee51a4e13b'/>
<id>urn:sha1:da4cfa6b442809fc99a6b75255a99eee51a4e13b</id>
<content type='text'>
There are still systems running which do not have any LAPIC or even
IOAPIC. Responsible MSRs for those do not exist and the systems are
crashing on trying to setup LAPIC.

This commit makes the APIC stuff able to switch off for those boards
which dont' have an LAPIC / IOAPIC.

Signed-off-by: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
</feed>
