starfive-tech/u-boot.git/arch/riscv/lib, branch rtthread_AMP

sysreset: provide SBI based sysreset driver

2023-02-02T11:11:45+00:00

Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Tested-by: Samuel Holland

riscv: lib: implement enable_caches for sifive cache

2021-09-07T02:34:29+00:00

The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li Reviewed-by: Rick Chen

common: board_r: support enable_caches for RISC-V

2021-09-07T02:34:29+00:00

The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li Reviewed-by: Rick Chen

riscv: show code leading to exception

2021-09-07T02:34:29+00:00

To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng Reviewed-by: Sean Anderson

efi_loader: add Linux magic to RISC-V crt0

2021-08-14T18:54:41+00:00

Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. MajorImageVersion = 1 indicates a kernel that can consume the EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with our initrddump.efi tool. Signed-off-by: Heinrich Schuchardt

riscv: booti: do not force relocation if force_reloc is not set

2021-07-21T08:38:26+00:00

If force_reloc flag is not set and booti is called for an address ouside RAM (i. e. QSPI NOR flash), we should honor that and not try to force relocation in a bogus fashion. Signed-off-by: Vitaly Wool Reviewed-by: Leo Yu-Chi Liang

riscv: andes_plic: Fix riscv_get_ipi() mask

2021-06-17T01:39:46+00:00

Current logic in riscv_get_ipi() for Andes PLICSW does not look correct. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi(). Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status") Signed-off-by: Bin Meng Reviewed-by: Rick Chen Tested-by: Rick Chen

riscv: Drop USE_SPL_FIT_GENERATOR

2021-05-19T09:01:51+00:00

Now that we have switched to binman to generate u-boot.itb for all RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can be dropped. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

riscv: Fix memmove and optimise memcpy when misalign

2021-05-17T08:47:33+00:00

At present U-Boot SPL fails to boot on SiFive Unleashed board, due to a load address misaligned exception happens when loading the FIT image in spl_load_simple_fit(). The exception happens in memmove() which is called by fdt_splice_(). Commit 8f0dc4cfd106 introduces an assembly version of memmove but it does take misalignment into account (it checks if length is a multiple of machine word size but pointers need also be aligned). As a result it will generate misaligned load/store for the majority of cases and causes significant performance regression on hardware that traps misaligned load/store and emulate them using firmware. The current behaviour of memcpy is that it checks if both src and dest pointers are co-aligned (aka congruent modular SZ_REG). If aligned, it will copy data word-by-word after first aligning pointers to word boundary. If src and dst are not co-aligned, however, byte-wise copy will be performed. This patch was taken from the Linux kernel patch [1], which has not been applied at the time being. It fixes the memmove and optimises memcpy for misaligned cases. It will first align destination pointer to word-boundary regardless whether src and dest are co-aligned or not. If they indeed are, then wordwise copy is performed. If they are not co-aligned, then it will load two adjacent words from src and use shifts to assemble a full machine word. Some additional assembly level micro-optimisation is also performed to ensure more instructions can be compressed (e.g. prefer a0 to t6). With this patch, U-Boot boots again on SiFive Unleashed board. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/ Fixes: 8f0dc4cfd106 ("riscv: assembler versions of memcpy, memmove, memset") Signed-off-by: Bin Meng

riscv: Fix arch_fixup_fdt always failing without /chosen

2021-05-17T08:46:33+00:00

If /chosen was missing, chosen_offset would never get updated with the new /chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes this by setting chosen_offset. In addition, log any errors from setting boot-hartid as well. Fixes: 5370478d1c7 ("riscv: Add boot hartid to device tree") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Atish Patra