starfive-tech/u-boot.git/arch/riscv/include/asm, branch rtthread_AMPStarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP2023-12-22T03:39:37+00:00spl: enable uart1 for RT-thread using2023-12-22T03:39:37+00:00Minda Chenminda.chen@starfivetech.com2023-11-10T01:26:19+00:00urn:sha1:b7cc16149a59929b51771c9bab6c14547a43e5e3
Set clock and uart1 pin (pin 43 and pin 45) in spl
stage, used as RT-thread console.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
riscv: cpu: jh7110: Add EEPROM support2023-11-29T02:46:35+00:00Hal Fenghal.feng@starfivetech.com2023-08-09T06:18:33+00:00urn:sha1:d5c8e632a1416092f93cfc3989d9969166292398
Add a header to easily use the EEPROM interface.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
gpio: starfive: Add SET_DS/SET_PULL/SET_SLEW support2023-07-26T10:35:38+00:00Samin Guosamin.guo@starfivetech.com2023-06-07T10:22:21+00:00urn:sha1:3566baaf467887df9c71a5185dc3f1808b5c923d
SET_DS/SET_PULL/SET_SLEW can configure the properties of the GPIO
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
board: starfive: copyright: Standardize the copyright format2023-04-23T03:19:47+00:00Yanhong Wangyanhong.wang@starfivetech.com2023-04-23T03:19:47+00:00urn:sha1:fe8426ebb03dc13a06758d2c4c0571e19b3c064a
Unify the content format of the copyright section
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
sysreset: provide SBI based sysreset driver2023-02-02T11:11:45+00:00Heinrich Schuchardtheinrich.schuchardt@canonical.com2021-09-12T19:11:46+00:00urn:sha1:b680cc70dc337d85e2931e6d65177b19729dc01a
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
riscv: add missing SBI extension definitions2023-02-02T11:11:40+00:00Heinrich Schuchardtheinrich.schuchardt@canonical.com2021-09-12T19:11:44+00:00urn:sha1:c9051a2bda68125f9c182a99f0274fc2f3b4ed32
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
board:starfive:evb: add get_chip_type2022-11-01T10:54:30+00:00Samin Guosamin.guo@starfivetech.com2022-11-01T08:19:48+00:00urn:sha1:0dbe3fb0be546f2be7adaee6baf6d550fbba4e26
Read the chip model from the rgpio3 and setenv "chip_vision"
1: jh7110B
0: JH7110A
defalut: JH7110A
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmii2022-11-01T10:54:21+00:00Samin Guosamin.guo@starfivetech.com2022-11-01T01:59:05+00:00urn:sha1:bd7deb0588459f36cf774ed58a419a7efbc9d5e4
JH7110B needs switch gmac0/1 tx to rgmii phy.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
arch: riscv: jh7110: add pll clk configuration for jh71102022-10-18T08:24:38+00:00Yan Hong Wangyanhong.wang@starfivetech.com2022-09-14T08:14:00+00:00urn:sha1:01bbc04d9d9c9e38e6dcc93b1e7dca57b5862c11
Add common interface to set and get pll clk information for jh7110 soc.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
SPL:starfive-jh7110: Modify the default division factor of sdcard clk2022-10-18T08:24:36+00:00yanhong.wangyanhong.wang@starfivetech.com2022-05-26T03:16:21+00:00urn:sha1:16178e355d396994e63546d552a5c75e4aad71c0
Modify the default division factor of sdcard clk to 4.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>