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<title>starfive-tech/u-boot.git/arch/riscv/include/asm/processor.h, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/'/>
<updated>2018-01-12T13:05:12+00:00</updated>
<entry>
<title>riscv: nx25: include: Add header files to support RISC-V</title>
<updated>2018-01-12T13:05:12+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2017-12-26T05:55:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=6020faf62c3bfb8677378d6c31e50f103bc06114'/>
<id>urn:sha1:6020faf62c3bfb8677378d6c31e50f103bc06114</id>
<content type='text'>
Add header files for RISC-V.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Signed-off-by: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
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