starfive-tech/u-boot.git/arch/riscv/cpu/cpu.c, branch rtthread_AMP

sysreset: provide SBI based sysreset driver

2023-02-02T11:11:45+00:00

Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Tested-by: Samuel Holland

treewide: Convert macro and uses of section(foo) to section("foo")

2021-05-24T18:21:30+00:00

This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún Reviewed-by: Bin Meng Reviewed-by: Simon Glass

riscv: cpu: Add callback to init each core

2021-05-05T08:11:22+00:00

Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan Reviewed-by: Rick Chen Reviewed-by: Bin Meng

riscv: Clear pending IPIs on initialization

2020-09-30T00:54:52+00:00

Even though we no longer call smp_function if an IPI was not sent by U-Boot, we still need to clear any IPIs which were pending from the execution environment. Otherwise, secondary harts will busy-wait in secondary_hart_loop, instead of relaxing. Along with the previous commit ("riscv: Use a valid bit to ignore already-pending IPIs"), this fixes SMP booting on the Kendryte K210. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen

riscv: Make SiFive HiFive Unleashed board boot again

2020-07-24T06:55:04+00:00

Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng Reviewed-by: Sean Anderson Tested-by: Leo Liang

riscv: Add option to support RISC-V privileged spec 1.9

2020-07-01T07:01:22+00:00

Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng

riscv: Clean up IPI initialization code

2020-07-01T07:01:22+00:00

The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23+00:00

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

common: Drop init.h from common header

2020-05-18T21:33:33+00:00

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

riscv: add run mode configuration for SPL

2019-08-26T08:07:42+00:00

U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel

starfive-tech/u-boot.git/arch/riscv/cpu/cpu.c, branch rtthread_AMP

sysreset: provide SBI based sysreset driver

treewide: Convert macro and uses of __section(foo) to __section("foo")

riscv: cpu: Add callback to init each core

riscv: Clear pending IPIs on initialization

riscv: Make SiFive HiFive Unleashed board boot again

riscv: Add option to support RISC-V privileged spec 1.9

riscv: Clean up IPI initialization code

common: Drop linux/bitops.h from common header

common: Drop init.h from common header

riscv: add run mode configuration for SPL

treewide: Convert macro and uses of section(foo) to section("foo")