<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/u-boot.git/arch/arm/lib, branch rtthread_AMP</title>
<subtitle>StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/u-boot.git/atom?h=rtthread_AMP'/>
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<updated>2021-08-08T15:59:01+00:00</updated>
<entry>
<title>Revert "arm: bootm: Disable LMB reservation for command line and board info on arm64"</title>
<updated>2021-08-08T15:59:01+00:00</updated>
<author>
<name>Jan Kiszka</name>
<email>jan.kiszka@siemens.com</email>
</author>
<published>2021-07-29T07:22:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=3823315cbedf930c52fe77452063ab6d62b157be'/>
<id>urn:sha1:3823315cbedf930c52fe77452063ab6d62b157be</id>
<content type='text'>
This reverts commit 2359fa7a87848626bcbd3399e92c657595880cd7.

While the goal is valid and there is surely unused memory in that area,
we also have a lot of crucial things still located at the top-of-memory
while running lmb_alloc_base. Such things are the page table (tlb_addr),
relocated U-Boot and the active stack. Possibly more. So this patch was
premature, we will need relocations of those things first if we want to
use the range.

Fixes booting on the IOT2050, but likely also on other boards. It got
stuck on relocating the FDT - over the relocated U-Boot code.

Signed-off-by: Jan Kiszka &lt;jan.kiszka@siemens.com&gt;
</content>
</entry>
<entry>
<title>global: Convert simple_strtoul() with hex to hextoul()</title>
<updated>2021-08-02T17:32:14+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-07-24T15:03:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=7e5f460ec457fe310156e399198a41eb0ce1e98c'/>
<id>urn:sha1:7e5f460ec457fe310156e399198a41eb0ce1e98c</id>
<content type='text'>
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.

Add a proper comment to simple_strtoul() while we are here.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: bootm: Disable LMB reservation for command line and board info on arm64</title>
<updated>2021-07-09T16:15:41+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2021-05-29T11:34:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=2359fa7a87848626bcbd3399e92c657595880cd7'/>
<id>urn:sha1:2359fa7a87848626bcbd3399e92c657595880cd7</id>
<content type='text'>
On arm64, board info is not applicable and kernel command line patched into
the DT, so the LMB reservation here makes no sense anymore. On legacy arm32,
this might still be necessary on systems which do not use DT or use legacy
ATAGS. Disable this LMB reservation on arm64.

This also permits Linux DT to specify reserved memory node at address close
to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after
boot, U-Boot will be no more, this is OK.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Hai Pham &lt;hai.pham.ud@renesas.com&gt;
Cc: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF is enable</title>
<updated>2021-07-09T15:36:12+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2021-02-24T12:48:42+00:00</published>
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<id>urn:sha1:ee0fbf4ef766f8d6a5a2d35906dfa2e3987f6f66</id>
<content type='text'>
Fix following compilation issue when SYS_DCACHE_OFF is enable:
drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour'

when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be
defined.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y</title>
<updated>2021-06-28T18:47:10+00:00</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2021-06-15T06:33:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=534f0fbd65203871c2b054096422a5d0f3346cb1'/>
<id>urn:sha1:534f0fbd65203871c2b054096422a5d0f3346cb1</id>
<content type='text'>
If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled,
wherever original env is placed anywhere, it should be relocated to
the right address.

Relocation offset gd-&gt;reloc_off is calculated with SYS_TEXT_BASE in
setup_reloc() and env address gd-&gt;env_addr is relocated by the offset in
initr_reloc_global_data().

gd-&gt;env_addr
  = (orig env) + gd-&gt;reloc_off
  = (orig env) + (gd-&gt;relocaddr - SYS_TEXT_BASE)

However, SYS_TEXT_BASE isn't always runtime base address when
POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to
wrong address. For example, if SYS_TEXT_BASE is zero, gd-&gt;env_addr is
out of memory location and memory exception will occur.

There is a difference between linked address such as SYS_TEXT_BASE and
runtime base address. In _main, the difference is calculated as
"run-vs-link" offset. The env_addr should also be added to the offset
to fix the address.

gd-&gt;env_addr
  = (orig env) + ("run-vs-link" offset)   + gd-&gt;reloc_off
  = (orig env) + (SYS_TEXT_BASE - _start) + (gd-&gt;relocaddr - SYS_TEXT_BASE)
  = (orig env) + (gd-&gt;relocaddr - _start)

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Tested-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>ARM: make LTO available</title>
<updated>2021-05-24T18:21:30+00:00</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:24:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=8f9696510afc2b52ebeba5d1db4883cf3331c206'/>
<id>urn:sha1:8f9696510afc2b52ebeba5d1db4883cf3331c206</id>
<content type='text'>
Make LTO available for ARM architecture.

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARM: fix LTO build for some thumb-interwork cases</title>
<updated>2021-05-24T18:21:30+00:00</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:24:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=e5fc9037dd3391a63cf6f6f7da015507ae12158d'/>
<id>urn:sha1:e5fc9037dd3391a63cf6f6f7da015507ae12158d</id>
<content type='text'>
Fix LTO build for some thumb-interwork usecases (such as for
da850evm_defconfig), where inline assmebly such as
  mrc p15,0,r2,c1,c0,0
causes the compiler to fail during LTO linking with
  Error: selected processor does not support `mrc p15,0,r2,c1,c0,0'
         in Thumb mode

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>treewide: Convert macro and uses of __section(foo) to __section("foo")</title>
<updated>2021-05-24T18:21:30+00:00</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:23:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=236f2ec43266cb4dabd320381498df6c9d80c82d'/>
<id>urn:sha1:236f2ec43266cb4dabd320381498df6c9d80c82d</id>
<content type='text'>
This commit does the same thing as Linux commit 33def8498fdd.

Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: zimage: Use correct symbol to hide messages in SPL</title>
<updated>2021-04-27T12:05:30+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-04-17T14:34:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=c2343695e309f2176817dfa836dd42fc6cecc7a3'/>
<id>urn:sha1:c2343695e309f2176817dfa836dd42fc6cecc7a3</id>
<content type='text'>
When zImage support was added to SPL, the messages were hidden to reduce
code size. However, the wrong config symbol was used. Since this file is
only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden.

Use the correct symbol so the messages are printed in U-Boot proper.
Also use IS_ENABLED to drop the #ifdef.

Fixes: 431889d6ad9a ("spl: zImage support in Falcon mode")
Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>arm64: gic-v3-its: Clear the Pending table before enabling LPIs</title>
<updated>2021-04-20T11:31:12+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2021-03-05T07:02:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/u-boot.git/commit/?id=6f6876a0c0304acc117d075344275d716f8a935a'/>
<id>urn:sha1:6f6876a0c0304acc117d075344275d716f8a935a</id>
<content type='text'>
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".

And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."

And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Tested-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt; # NXP LS1028A
Reviewed-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
</feed>
