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In starfive_gpio_direction_output() readl() is called twice to read the
gpio direction register. The result of the first read is discarded.
Remove the redundant read.
Fixes: 908be1b85c8f ("gpio/starfive: add gpio driver and support gpio reset")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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sbi_pmu_ctr_cfg_match() receives data from a lower privilege level mode.
We must catch maliciously wrong values.
We already check against total_ctrs. But we do not check that total_ctrs is
less than SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX.
Check that the number of hardware counters is in the valid range.
Addresses-Coverity-ID: 1566114 Out-of-bounds write
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
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The define is hard to read. The continue statement does not do what was
intended.
* Remove do {} while (false);
* Change the name to set_multi_letter_ext
- Other local macros are lower case too.
- Refer to the fact that this is only used for multi-letter extensions.
Addresses-Coverity-ID: 1568359 Unexpected control flow
Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA string in FDT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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hart_exts == NULL can only occur if offset and node address lead to an
overflow resulting in exactly NULL. As we don't catch other values of
overflow it does not make sense to treat this one as special.
Addresses-Coverity-ID: 1568355 Logically dead code
Addresses-Coverity-ID: 1568358 Logically dead code
Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions() implementation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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'1' is a 32 bit integer. When shifting it by more than 31 bits it becomes
zero and we get an incorrect return value.
Addresses-Coverity-ID: 1568356 Bad bit shift operation
Fixes: 296e70d69da7 ("lib: sbi: Extend sbi_hartmask to support both hartid and hartindex")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.
With this update, both regions will become M-mode only read/write
regions in the root domain.
Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
p/x $pmpcfg0
$1 = {0x1f9b9b9d9b1e00,
pmp0cfg = {0x0},
L--AAXWR
pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1)
pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff
pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff
pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff
pmp7cfg = {0x0 }}
The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
p/x $pmpcfg0
$1 = {0x1f181818181b,
L--AAXWR
pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1)
pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff
pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff
pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff
pmp6cfg = {0x0 }}
Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The added memory region should start from the base address.
Otherwise, the range will be shifted by reg_offset and not
able to merge consecutive NAPOT regions in the root domain,
resulting in wasted PMP entries.
Fixes: e8bc1621 ("lib: utils/serial: Add shared regions for
serial drivers")
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The syscon region used by OpenSBI should be marked as a shared
read-write region between M-mode and SU-mode.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
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The serial driver regions used by OpenSBI should be marked as a shared
read-write regions between M-mode and SU-mode as those are accessed
by earlycon and the corresponding tty serial drivers running in 'S' mode.
When the smepmp extension is enabled, PMP entries for these shared regions
will get programmed.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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Based on sections 4.c and 4.d in Ch.2 of the Smepmp spec the PMP entries
must be programmed as below:
1. Program M-only entries
2. Enable mseccfg.MML
3. Program shared-region entries
4. Program SU-only entries
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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The Smepmp read-only shared region must have pmpcfg.L, pmpcfg.R,
pmpcfg.W, and pmpcfg.X bits set so sbi_hart_get_smepmp_flags()
must return pmp_flags accordingly.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
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The mseccfg.MML bit is a sticky bit which remains unchanged once set
so no need to clear it in sbi_hart_smepmp_configure().
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
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Let us factor-out Smepmp configuaration as separate function so
that code is more readable.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
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The sbi_hartmask_for_each_hart() macro is slow and has only one user
so let us completely remove the sbi_hartmask_for_each_hart() macro.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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Let us maximize the use of HART index in sbi_domain because hartindex
based hartmask access and sbi_scratch lookup is faster.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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The sbi_scratch_last_hartid() macro is not of much use on platforms
with really sparse hartids so let us replace use of this macro with
other approaches.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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Let us prefer hartindex over hartid in IPI framework which in-turn
forces IPI users to also prefer hartindex.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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The sbi_hartid_to_scratch() involves translating hartid to hartindex
which is expensive so let's use sbi_hartindex_to_scratch() instead.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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Currently, the sbi_hartmask is indexed by hartid which puts a
limit on hartid to be less than SBI_HARTMASK_MAX_BITS.
We extend the sbi_hartmask implementation to use hartindex and
support updating sbi_hartmask using hartid. This removes the
limit on hartid and existing code works largely unmodified.
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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The hartid to hartindex mapping is now tracked in sbi_scratch so we
don't need sbi_platform_hart_index() and sbi_platform_hart_invalid()
functions hence let us remove them.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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We introduce HART index and related helper functions in sbi_scratch
where HART index is contiguous and each HART index maps to a physical
HART id such that 0 <= HART index and HART index < SBI_HARTMASK_MAX_BITS.
The HART index to HART id mapping follows the index2id mapping provided
by the platform. If the platform does not provide index2id mapping then
identity mapping is assumed.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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If the system is defined from tlb_fifo_num_entries, the scratch may be
too small to hold the fifo, so it is alloc through the heap.
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Xing Xiaoguang <xiaoguang.xing@sophgo.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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For some platforms with a particularly high number of harts, if the
tlb fifo is too small, it case harts to wait. Platforms should be
allowed to specify the size of the tlb fifo.
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Xing Xiaoguang <xiaoguang.xing@sophgo.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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After the hardware hpm counter is stopped, it should not raise any new
interrupt as it is already stopped. So add the hw_counter_disable_irq
callback to allow the custom pmu device to control this behavior.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Samuel Holland <samuel@sholland.org>
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When detecting features of PMU, the hpm counter may be written to some
value, this will cause some unexpected behavior in some cases. So ensure
the hpm counter is updated before starting the counter and the related
interrupt.
Signed-off-by: Haijiao Liu <haijiao.liu@sophgo.com>
Co-authored-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Samuel Holland <samuel@sholland.org>
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The previous definition had the assumption that the machine word length
is equal to the word length of LONG. Remove this assumption and add a
static check to prevent errors in subsequent modifications.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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After supporting noncontigous hpm event and counters in opensbi, the
number of hpm counters can be calculated by the mhpm_mask. So this field
is unnecessary and can be removed to save some space.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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This adds the support for ISA extension smcntrpmf. When some inhibit flags
are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI
sets the appropriate values correspondingly.
Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
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Cycle and instructions are hardware events instead of firmware ones. Fix
the typo in the name of this function.
Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Anup patel <anup@brainfault.org>
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Currently, the fdt_parse_isa_extensions() tries to parse the ISA
string once for each HART. This ISA string parsing can fail for
secondary HARTs if the FDT memory is already overwritten by the
supervisor OS.
To tackle this issue, we improve the fdt_parse_isa_extensions()
implementation to pre-parse ISA string for all HARTs during
cold boot.
Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA
string in FDT")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-By: Mayuresh Chitale<mchitale@ventanamicro.com>
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Platforms may implement hpm events/counters non contiguously but the current
implementation assumes them to be always contigous. Add a bitmap that
captures the hpm events/counters as implemented in the hardware and use
it to set the max limit of hardware counters visible to the OS. Counters
not implemented in the hardware can't be used by the OS because those
wont be described in the DT.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The functionality of SiFive Test reset driver is easily available
through Syscon reset driver so let us remove the SiFive Test driver.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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Let us have common FDT based reset driver for syscon reboot and
poweroff. The device tree bindings for syscon reboot and poweroff
are already available in the Linux kernel sources.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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Let us add a simple FDT based system regmap driver which follows the
device tree bindings already defined in the Linux kernel.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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We add a simple FDT based regmap framework which is built on top of
generic regmap library. The phandle of FDT regmap DT node is treated
as unique regmap ID. The FDT based regmap drivers will be probed
on-demand from fdt_regmap_get_by_phandle() and fdt_regmap_get()
called by the regmap client drivers.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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We add generic regmap access library which is independent of
hardware description format (FDT or ACPI). The OpenSBI platform
support or regmap drivers can register regmap instances which
can be discovered by different regmap clients based on the
unique ID of regmap instances.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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The "driver" pointer in struct i2c_adapter is not used anywhere
so let us remove it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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commit 68e66106120f ("SUSP: Add SBI_ERR_DENIED") of the SBI spec adds
a new error code, SBI_ERR_DENIED, which is returned when entry criteria
has not be meant. Update the system suspend implementation to return
this error when it has detected that not all harts are in the STOPPED
state.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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License identifiers should be machine readable.
According to the SPDX v2.3.0 specification annex E parentheses are not
used in the SPDX identifier field when specifying multiple licenses [1].
[1] https://spdx.github.io/spdx-spec/v2.3/using-SPDX-short-identifiers-in-source-files/
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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With Smepmp enabled, it is necessary for shared memory from
S/U mode to be mapped/unmapped before and after read/write
of the memory region. This patch maps the debug console
shared memory before accessing it.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When Smepmp is enabled, M-mode will need to map/unmap the
shared memory before it can read/write to it. This patch
adds functions to create dynamic short-lived mappings.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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- If Smepmp is enabled, the access flags of an entry are determined based on
truth table defined in Smepmp.
- First PMP entry (index 0) is reserved.
- Existing boot PMP entries start from index 1.
- Since enabling Smepmp revokes the access privileges of the M-mode software
on S/U-mode region, first PMP entry is used to map/unmap the shared memory
between M and S/U-mode. This allows a temporary access window for the M-mode
software to read/write to S/U-mode memory region.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Configure PMP at last when all other initializations have been done.
Because if SMEPMP is detected, M-mode access to the S/U space will be
rescinded.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Since pmp entries have implicit priority on index, previous entries will
deny access to SU on M-mode region. Also, M-mode will not have access to
SU region while previous entries will allow access to M-mode regions.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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- Add function to parse ISA string in FDT.
- Set Smepmp feature bit in extensions if "smepmp" string is found in ISA string.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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- Add Smepmp as extension in sbi_hart_extensions enum
- Return "smepmp" string for Smepmp extension from sbi_hart_extension_id2string
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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- Add a function to disable a given PMP entry.
- Add a function to check if a given entry is disabled.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Currently, we see following compile error in the designeware GPIO driver
for RV32 systems:
lib/utils/gpio/fdt_gpio_designware.c:115:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
115 | chip->dr = (void *)addr + (bank * 0xc);
| ^
lib/utils/gpio/fdt_gpio_designware.c:116:21: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
116 | chip->ext = (void *)addr + (bank * 4) + 0x50;
We fix the above error using an explicit type-cast to 'unsigned long'.
Fixes: 7828eebaaa77 ("gpio/desginware: add Synopsys DesignWare APB GPIO support")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
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Fix special case: sbi_snprintf(out, out_len, ...) when out_len equal
1, The previous code will not fill the buffer with any char.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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A single scan of the format char may add multiple characters to the
tbuf, causing a buffer overflow. You should check if tbuf is full in
printc so that it does not cause a buffer overflow.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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